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VHDL - select configuration as a top-level for synthesize in Xlinx |
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Hi,
I'm wondering that is there any way to use configuration clause outside the architecture declarative part as a top-level for synthesize? E.g. as a separate file. I have had no problem doing it this way in Aldec, but it seems XST doesn't bind the correct component if I do it this way. In fact, XST completely overlooks my configuration statement if I declare it as a separate file. My guess is I need to specify something with XST's settings or give the configuration statement file a special extension name. I looked through the forum to no avail. If anyone does know how to do this, I'd be appreciate if you can tell me. Thanks, -ice ps. I'm using Xilinx XST 9.1 as a synthesis tool, so if newer version fixes this problem (or include this feature) please let me know. ice |
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