Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > ISE 10.1 and Timing Simulation Errors

Thread Tools

ISE 10.1 and Timing Simulation Errors

Posts: n/a
On Feb 27, 4:26*pm, john <(E-Mail Removed)> wrote:
> Hi,
> What does P&R'ed mean ? So, both behavorial and timing simulaion are
> important to program a FPGA? Am I right?
> John

P&R'ed = place and routed.

you technically dont need to do either. but its a good idea that you
Reply With Quote

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off

Similar Threads
Thread Thread Starter Forum Replies Last Post
Problem with post-route simulation / timing simulation jasperng VHDL 0 11-27-2008 06:23 AM
Timing constraint on ISE Yannick VHDL 0 07-31-2008 03:03 PM
timing in ISE Simulator samehsh VHDL 0 06-15-2008 04:08 PM
Timing details during synthesis in Xilinx ISE Thunder VHDL 2 06-29-2007 10:56 AM
ISE timing report spartan VHDL 3 07-22-2004 03:17 AM