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VHDL - one hot state machine using for/generate

 
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Old 02-20-2009, 04:23 PM   #1
Default one hot state machine using for/generate


I'm trying to create the states for a state machine using for/generate and there is an issue that I hope somebody could help with.

Below is a code snippet used to generate one-hot states:
type state_reg_type is array (NSTATE-1 downto 0) of std_logic_vector (NSTATE-1 downto 0);
signal bist_ctrl_state : state_reg_type;
begin
gen_state_values :
for i in 0 to NSTATE-1 generate
bist_ctrl_state(i) <= to_stdlogicvector(shift_in sll i);
end generate;

However when time comes to code the next state control if/elsif/else has to be used. When a case is tried the following error is produced:
** Error: ./ctrl.vhd(8: Case choice must be a locally static expression

I take it this means that bist_ctrl_state has to be declared as a constant.

Is there a way to declare the state values using a generate that would allow next state control to be performed using a case?

Thanks


amdti
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