|
|
|
|
02-20-2009, 04:57 AM
|
#1 |
need vhdl code
i need vhd for genetic algorithm in evolvable hardware design.
kasthuri.m92@gmail.com |
|
|
|
02-20-2009, 05:53 AM
|
#2 |
|
Posts: n/a
|
Re: need vhdl code
On Feb 19, 11:57*pm, kasthuri....@gmail.com wrote:
> * i need vhd for genetic algorithm in evolvable hardware design. Google found 929 results for the search "genetic algorithm" +"evolvable hardware" +vhdl Can you be a little bit more specific? kennheinrich@sympatico.ca |
|
|
|
02-20-2009, 08:57 AM
|
#3 |
|
Posts: n/a
|
Re: need vhdl code
On 20 Feb, 04:57, kasthuri....@gmail.com wrote:
> * i need vhd for genetic algorithm in evolvable hardware design. library ieee; use ieee.std_logic_1164.all; entity evolvable_hardware is port ( reset : in std_logic; clk : in std_logic; d : in std_logic; q : out std_logic; ); end entity evolvable_hardware; architecture evolve of evolvable_hardware is begin reg_proc : process(clk) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process; end architecture evolve; I bet something like this could eventually evolve into an FFT? Tricky |
|
|
|
02-20-2009, 12:03 PM
|
#4 |
|
Posts: n/a
|
Re: need vhdl code
On 20 Feb, 08:57, Tricky <Trickyh...@gmail.com> wrote:
> On 20 Feb, 04:57, kasthuri....@gmail.com wrote: > > > i need vhd for genetic algorithm in evolvable hardware design. > > library ieee; > use ieee.std_logic_1164.all; > > entity evolvable_hardware is > port ( > reset : in std_logic; > clk : in std_logic; > d : in std_logic; dsex : in std_logic; > q : out std_logic; > ); > end entity evolvable_hardware; > > architecture evolve of evolvable_hardware is > begin > > reg_proc : process(clk) > begin > if reset = '1' then > q <= '0'; > elsif rising_edge(clk) then if sex_prob = '1' then q <= dsex; else > q <= (d XOR mutate_prob) ; end if; > end if; > end process; > > end architecture evolve; > > I bet something like this could eventually evolve into an FFT? What kind of FET? cheers jacko Jacko |
|
|
