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VHDL - Compile time

 
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Old 02-19-2009, 11:20 PM   #1
Default Compile time


Hi, sorry if I may be ot, but I just need a simple answer: in many
benchmark I found the result of the compile time used for a particular
core. Now, compile time what does it means? Syntesys, optimization and
mapping or syntesys, optimization, mapping and p&r?

Thanks, Mattia


gervaz
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