Illegal sequential statement error

Hi everyone,
I am new to VHDL.... This is the code i did... Am getting 'Illegal sequential statement' error... Kindly help me out... here is the code...

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity encrypt1 is
port(
Ct : out unsigned(47 downto 0);
p : in unsigned(47 downto 0)
);
end entity encrypt1;

architecture trans of encrypt1 is
component sb1 is
port (
y : out unsigned(23 DOWNTO 0);
x : in unsigned(23 DOWNTO 0)
);
end component;

component bx1 is
port (
z : out unsigned(23 DOWNTO 0);
y : in unsigned(23 DOWNTO 0);
x : in unsigned(23 DOWNTO 0)
);
end component;

component am1 is
port (
z : out unsigned(23 DOWNTO 0);
y : in unsigned(23 DOWNTO 0);
x : in unsigned(23 DOWNTO 0)
);
end component;

component wr1 is
port (
w : out unsigned(23 DOWNTO 0);
z : in unsigned(23 DOWNTO 0)
);
end component;

component br1 is
port (
y : out unsigned(23 DOWNTO 0);
x : in unsigned(23 DOWNTO 0)
);
end component;

component key1 is
port(
q : out unsigned(47 downto 0);
r : in unsigned(47 downto 0);
s : in unsigned(23 downto 0)
);
end component;

signal i : integer;
signal ci : unsigned(23 downto 0);
signal k : unsigned(47 downto 0);
signal ki : unsigned(47 downto 0);
signal a : unsigned(23 downto 0);
signal b : unsigned(23 downto 0);
signal c : unsigned(23 downto 0);
signal d : unsigned(23 downto 0);
signal e : unsigned(23 downto 0);
signal kr : unsigned(23 downto 0);
signal kl : unsigned(23 downto 0);
signal p1 : unsigned(47 downto 0);

begin

process

variable ri : unsigned(47 downto 0);
variable rx : unsigned(23 downto 0);
begin
ri(47 downto 24) := p(47 downto 24);
ri(23 downto 0) := p(23 downto 0);

loop1 : for i in 1 to 25 generate
p1 <= ri;
K1 : key1
port map(
q => ki,
r => k,
s => ci
);

k<=ki;
kr(23 downto 0)<=ki(23 downto 0);
kl(23 downto 0)<=ki(47 downto 24);

A2 : am1
port map(
z => a,
x => p1(23 downto 0),
y => kr
);

S2 : sb1
port map(
y => b,
x => a
);

R2 : br1
port map(
y => c,
x => b
);

W2 : wr1
port map(
w => d,
z => p1(47 downto 24)
);

X2 : bx1
port map(
z => e,
x => d,
y => b
);
rx := ri(23 downto 0);
ri(47 downto 24) := rx;
ri(23 downto 0) := e;
end generate;


loop2 : for i in 26 to 50 generate

p1 <= ri;
K2 : key1
port map(
q => ki,
r => k,
s => ci
);

k<=ki;
kr(23 downto 0)<=ki(23 downto 0);
kl(23 downto 0)<=ki(47 downto 24);

A3 : am1
port map(
z => a,
x => p1(23 downto 0),
y => kr
);

S3 : sb1
port map(
y => b,
x => a
);

R3 : br1
port map(
y => c,
x => b
);

W3 : wr1
port map(
w => d,
z => p1(47 downto 24)
);

X3 : bx1
port map(
z => e,
x => d,
y => b
);
rx := ri(23 downto 0);
ri(47 downto 24) := rx;
ri(23 downto 0) := e;

end generate;
Ct <= ri;

end process;
end;

Thanks in advance...

shankar.dante

[eliascm]

The first thing I noticed is that you have declared components and then instantiated them without first coding an entity/architecture for each component. How can the compiler generate code for a component without VHDL code describing its operation? Read up on the proper way use components and this will solve many, if not all, of your problems.

eliascm