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one hot machine without elsif

 
 
KJ
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      02-19-2009
On Feb 18, 5:28*pm, "Brad Smallridge" <(E-Mail Removed)>
wrote:
> > I agree with Tricky.
> > Unless you rewrite the code using an enumeration,
> > there are no pretty options.
> > * * * -- Mike Treseler

>
> I am not sure what I gain from enumeration.
>


Enumeration will imply mutually exclusivity, in your original post you
said "although I can be very sure that the states are mutually
exclusive by design"...'very sure' is not really the same thing. You
may already be aware (but in case you're not), the individual cases do
not have to represent the actions of a single enumeration. As an
example...
case xyz is
when This | That => -- Do things when 'This' or 'That'
when Some_Other_Thing => -- Do when 'Some_Other_Thing'
...
end case;

> I'm not happy with VHDL for not having a easy
> method for turning off these logic chains. And
> case is only good for single signals.
>


In order to express logic that you can be "very sure that the states
are mutually exclusive by design" but the case statement doesn't quite
do it for you, the other method is to express it in a sum of products
form.

From your original post...
if state(33 to 36)>0 then
mem_out<=a;
elsif state(37)>0 then
mem_out<=b;

If you know for darn sure that the two conditions being tested are
mutually exclusive, then you can express this as
mem_out <= To_Std_Logic(state(33 to 36)>0) and a
or To_Std_Logic(state(37)>0) and b;

I've taken some liberties here just to clarify the point. First
'To_Std_Logic' would be a function that simply converts a boolean to a
std_logic signal. Second, as written here 'a' and 'b' would be
std_logic although I know you're probably more interested in vector
types. But you can also override the 'and' function with one of the
form

function "and" (L: std_logic; R: std_logic_vector) return
std_logic_vector

Or, if you don't want to override "and" you could create another
function that takes in a std_logic and a vector, zeroing out or
passing through the bits based on the value of the std_logic
parameter.

The basic idea I'm trying to get across is that structuring your
equations in the sum of products form allows for arbitrarily complex
conditions to be evaluated and applied and does not create any
priority encoding logic of any sort. If the conditions you specify do
not happen to actually be mutually exclusive (i.e. 'very sure' was
wrong) all that happens is that two of the 'or' terms fire (which of
course will likely corrupt the output) but that's because you erred in
assuming that things were mutually exclusive when they really were
not.

> I think I'll take this to the FPGA group who
> may be more sensitive to synthesis issues.
>

I think you'll get better answers here myself.

Kevin Jennings
 
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