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Using a memory initialization file

 
 
Walther
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      02-16-2009
I apologize in advance for what is probably a really stupid beginners
question.

I am currently busy with an assignment for my one course. We are
required to implement the RiSC-16 sequential CPU in VHDL using Quartus
II. We are however not allowed to use megafunctions or other altera
supplied libraries.

Now, my CPU is pretty much done. I am however struggling to figure out
how to link a MIF file to a specific memory component (Namely to my
instruction memory component).

Does anybody know how to do this, and could you please give a nice
step by step explanation on how to do it.

Thanks in advance.
Walther
 
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Aiken
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      02-16-2009
do you do it in your simulation program for example Modelsim.
After you start your simluation at time "0". you can update the memory
content.

Aiken

On Feb 16, 3:22*pm, Walther <(E-Mail Removed)> wrote:
> I apologize in advance for what is probably a really stupid beginners
> question.
>
> I am currently busy with an assignment for my one course. We are
> required to implement the RiSC-16 sequential CPU in VHDL using Quartus
> II. We are however not allowed to use megafunctions or other altera
> supplied libraries.
>
> Now, my CPU is pretty much done. I am however struggling to figure out
> how to link a MIF file to a specific memory component (Namely to my
> instruction memory component).
>
> Does anybody know how to do this, and could you please give a nice
> step by step explanation on how to do it.
>
> Thanks in advance.
> Walther


 
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Mike Treseler
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      02-16-2009
Walther wrote:

> I am currently busy with an assignment for my one course. We are
> required to implement the RiSC-16 sequential CPU in VHDL using Quartus
> II. We are however not allowed to use megafunctions or other altera
> supplied libraries.


That is a good thing.
You won't learn to write code using megafunctions.

> Now, my CPU is pretty much done. I am however struggling to figure out
> how to link a MIF file to a specific memory component (Namely to my
> instruction memory component).


Maybe you don't need a mif file.
Why not infer a rom from a vhdl constant array?
Something like this
http://mysite.verizon.net/miketreseler/sync_rom.vhd

-- Mike Treseler
 
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Walther
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      02-17-2009
On Feb 17, 1:30*am, Mike Treseler <(E-Mail Removed)> wrote:
> Walther wrote:
> > I am currently busy with an assignment for my one course. We are
> > required to implement the RiSC-16 sequential CPU in VHDL using Quartus
> > II. We are however not allowed to use megafunctions or other altera
> > supplied libraries.

>
> That is a good thing.
> You won't learn to write code using *megafunctions.
>
> > Now, my CPU is pretty much done. I am however struggling to figure out
> > how to link a MIF file to a specific memory component (Namely to my
> > instruction memory component).

>
> Maybe you don't need a mif file.
> Why not infer a rom from a vhdl constant array?
> Something like thishttp://mysite.verizon.net/miketreseler/sync_rom.vhd
>
> * *-- Mike Treseler


Thanks Mike

That is what I'm currently doing to test the CPU. However, I would
like to be able to easily load other test programs without needing to
retype all the instructions and recompiling. If I can't initialise the
memory from an external file, then it's not a train smash, but it
would make verification and simulation much easier.

Walther
 
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Tricky
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      02-17-2009
On 17 Feb, 06:43, Walther <(E-Mail Removed)> wrote:
> On Feb 17, 1:30*am, Mike Treseler <(E-Mail Removed)> wrote:
>
>
>
> > Walther wrote:
> > > I am currently busy with an assignment for my one course. We are
> > > required to implement the RiSC-16 sequential CPU in VHDL using Quartus
> > > II. We are however not allowed to use megafunctions or other altera
> > > supplied libraries.

>
> > That is a good thing.
> > You won't learn to write code using *megafunctions.

>
> > > Now, my CPU is pretty much done. I am however struggling to figure out
> > > how to link a MIF file to a specific memory component (Namely to my
> > > instruction memory component).

>
> > Maybe you don't need a mif file.
> > Why not infer a rom from a vhdl constant array?
> > Something like thishttp://mysite.verizon.net/miketreseler/sync_rom.vhd

>
> > * *-- Mike Treseler

>
> Thanks Mike
>
> That is what I'm currently doing to test the CPU. However, I would
> like to be able to easily load other test programs without needing to
> retype all the instructions and recompiling. If I can't initialise the
> memory from an external file, then it's not a train smash, but it
> would make verification and simulation much easier.
>
> Walther


Then you will probably have to write a script to write the constant
array for you, to then copy/paste into your code - or for even more
clvereness, actaully re-write the constant declaration for you inside
the VHDL.

Otherwise, you will have to write your own MIF interpreter, which will
probably be just as involved as the above idea.
 
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Barry
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      02-17-2009
On Feb 16, 12:22*pm, Walther <(E-Mail Removed)> wrote:
> I apologize in advance for what is probably a really stupid beginners
> question.
>
> I am currently busy with an assignment for my one course. We are
> required to implement the RiSC-16 sequential CPU in VHDL using Quartus
> II. We are however not allowed to use megafunctions or other altera
> supplied libraries.
>
> Now, my CPU is pretty much done. I am however struggling to figure out
> how to link a MIF file to a specific memory component (Namely to my
> instruction memory component).
>
> Does anybody know how to do this, and could you please give a nice
> step by step explanation on how to do it.
>
> Thanks in advance.
> Walther


I only used a mif file once, when I used Xilinx CoreGen to create a
ROM. I just dragged the mif file into my testbench directory (which
is the directory I opened in ModelSim to run the simulation), and it
picked up the mif file automatically.

Barry
 
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PlayDough
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      02-17-2009
On Feb 17, 1:12*am, Tricky <(E-Mail Removed)> wrote:
> Then you will probably have to write a script to write the constant
> array for you, to then copy/paste into your code - or for even more
> clvereness, actaully re-write the constant declaration for you inside
> the VHDL.


Or rather, write a Perl script or C program to convert the MIF into a
format that is easy to import. It is quite easy to write some VHDL to
read in a simple list of vectors from a file to populate your RAM. I
recommend you look at the source code for the Altera primitive RAM
models. I've never used Altera, but both Xilinx and Actel models are
capable of being initialized from a file, and the code is very easy to
understand.

I've never heard of MIF until this thread, but it looks very easy to
parse. (I used the reference at the Altera site:
http://www.altera.com/support/softwa...def_mif..html).
And considering that Altera is the source, their models probably read
MIF files. So you can scab the code from their models.

> Otherwise, you will have to write your own MIF interpreter, which will
> probably be just as involved as the above idea.


Doing this in VHDL/Verilog (though perhaps with the PLI it could be
fairly simple) would be more difficult than a Perl script/C code to
generate the constant table. For a class, I recommend a script based
approach.

Pete
 
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Amal
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      02-18-2009
On Feb 17, 1:15*pm, PlayDough <(E-Mail Removed)> wrote:
> On Feb 17, 1:12*am, Tricky <(E-Mail Removed)> wrote:
>
> > Then you will probably have to write a script to write the constant
> > array for you, to then copy/paste into your code - or for even more
> > clvereness, actaully re-write the constant declaration for you inside
> > the VHDL.

>
> Or rather, write a Perl script or C program to convert the MIF into a
> format that is easy to import. *It is quite easy to write some VHDL to
> read in a simple list of vectors from a file to populate your RAM. *I
> recommend you look at the source code for the Altera primitive RAM
> models. *I've never used Altera, but both Xilinx and Actel models are
> capable of being initialized from a file, and the code is very easy to
> understand.
>
> I've never heard of MIF until this thread, but it looks very easy to
> parse. *(I used the reference at the Altera site:http://www.altera.com/support/softwa...glossary/d...).
> And considering that Altera is the source, their models probably read
> MIF files. *So you can scab the code from their models.
>
> > Otherwise, you will have to write your own MIF interpreter, which will
> > probably be just as involved as the above idea.

>
> Doing this in VHDL/Verilog (though perhaps with the PLI it could be
> fairly simple) would be more difficult than a Perl script/C code to
> generate the constant table. *For a class, I recommend a script based
> approach.
>
> Pete


If you are using Synplicity and do not mind using Verilog for your
ROMs, you can use $readmemb, $readmemh tasks in an initial block to
read the contents of ROM from the file. This way you can have a
portable ROM implementation between FPGA and ASIC versions. For FPGA
version, $readmemb, and $redmemh use the same memory data file as your
ASIC foundry's ROM data file.

Check and see if Quartus supports $readmemb or $readmemh for
synthesis.

-- Amal
 
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Walther
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      02-19-2009
On Feb 18, 5:31*pm, Amal <(E-Mail Removed)> wrote:
> On Feb 17, 1:15*pm, PlayDough <(E-Mail Removed)> wrote:
>
>
>
> > On Feb 17, 1:12*am, Tricky <(E-Mail Removed)> wrote:

>
> > > Then you will probably have to write a script to write the constant
> > > array for you, to then copy/paste into your code - or for even more
> > > clvereness, actaully re-write the constant declaration for you inside
> > > the VHDL.

>
> > Or rather, write a Perl script or C program to convert the MIF into a
> > format that is easy to import. *It is quite easy to write some VHDL to
> > read in a simple list of vectors from a file to populate your RAM. *I
> > recommend you look at the source code for the Altera primitive RAM
> > models. *I've never used Altera, but both Xilinx and Actel models are
> > capable of being initialized from a file, and the code is very easy to
> > understand.

>
> > I've never heard of MIF until this thread, but it looks very easy to
> > parse. *(I used the reference at the Altera site:http://www.altera.com/support/softwa...glossary/d...).
> > And considering that Altera is the source, their models probably read
> > MIF files. *So you can scab the code from their models.

>
> > > Otherwise, you will have to write your own MIF interpreter, which will
> > > probably be just as involved as the above idea.

>
> > Doing this in VHDL/Verilog (though perhaps with the PLI it could be
> > fairly simple) would be more difficult than a Perl script/C code to
> > generate the constant table. *For a class, I recommend a script based
> > approach.

>
> > Pete

>
> If you are using Synplicity and do not mind using Verilog for your
> ROMs, you can use $readmemb, $readmemh tasks in an initial block to
> read the contents of ROM from the file. *This way you can have a
> portable ROM implementation between FPGA and ASIC versions. *For FPGA
> version, $readmemb, and $redmemh use the same memory data file as your
> ASIC foundry's ROM data file.
>
> Check and see if Quartus supports $readmemb or $readmemh for
> synthesis.
>
> -- Amal


Thanks for all the help. I decided to write a little script that
transforms the output of the assembler into a VHDL array format.

Works quite well.

Amal: We have to use Quartus, and VHDL (No Verilog)

- Walther
 
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