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arrrrg!

 
 
Ken Cecka
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      02-14-2009
I just spent all afternoon trying to figure out why isimwave (the xilinx simluation waveform viewer) was drawing my state machine value in red for certain states.

I believe I've finally tracked it down: if my state name contains the letter 'X', xilinx draws it in red. For example, with the following states:

TYPE state_type IS ( STATE1, STATE2X );

Any time a signal has the value STATE1, it will be drawn in green. If it has the value STATE2X, it will be drawn in red.

Posting this partly to see if others can confirm this behavior and/or give a better explanation, and partly to get it documented somewhere for the next poor soul who wonders what's causing there state machine to go into an invalid state.

Also, I'm guessing this should be considered a bug in isimwave - is there anything in the language specification that says you can't use the letter X in your enumerated state names?

Ken
 
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kennheinrich@sympatico.ca
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      02-14-2009
On Feb 14, 12:01*am, Ken Cecka <(E-Mail Removed)> wrote:
> I just spent all afternoon trying to figure out why isimwave (the xilinx simluation waveform viewer) was drawing my state machine value in red for certain states.
>
> I believe I've finally tracked it down: if my state name contains the letter 'X', xilinx draws it in red. *For example, with the following states:
>
> * TYPE state_type IS ( STATE1, STATE2X );
>
> Any time a signal has the value STATE1, it will be drawn in green. *If it has the value STATE2X, it will be drawn in red.
>
> Posting this partly to see if others can confirm this behavior and/or give a better explanation, and partly to get it documented somewhere for the next poor soul who wonders what's causing there state machine to go into an invalid state.
>
> Also, * I'm guessing this should be considered a bug in isimwave - is there anything in the language specification that says you can't use the letter X in your enumerated state names?
>
> Ken


There's nothing that says you can't use the letter "X" in your enums.
Perfect examples are in the language already: the simple character
'X' , as well as the names STX and ETX, are members of the CHARACTER
enum.

- Kenn
 
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Al Muliman
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      02-14-2009
On 14-02-2009 06:01, Ken Cecka wrote:
> Any time a signal has the value STATE1, it will be drawn in green.
> If it has the value STATE2X, it will be drawn in red.
>
> Posting this partly to see if others can confirm this behavior


Running ISIM 10.1.03 WebPack on Windows Vista Home Basic, I can confirm.
But surely that is a feature rather than a bug

> and/or give a better explanation,


I cannot. But then what do I know.

 
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Al Muliman
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      02-14-2009
On 14-02-2009 08:29, Al Muliman wrote:
> On 14-02-2009 06:01, Ken Cecka wrote:
>> Any time a signal has the value STATE1, it will be drawn in green.
> > If it has the value STATE2X, it will be drawn in red.
>>
>> Posting this partly to see if others can confirm this behavior

>
> Running ISIM 10.1.03 WebPack on Windows Vista Home Basic, I can confirm.
> But surely that is a feature rather than a bug
>


That feature also involves states named "FUNC". My state is in a shared
(to see it in Isim waveform viewer) variable.


When I rename the state to "FANC", it is green. When I rename to "UANC"
it is red again. The letter "U" seems to do the trick also. Renaming to
"XANC" also makes it red. So the position does not matter. Playing
around with the color coding reveals that it is considered an undefined
value in all cases.

If this is an undocumented feature then I suppose it is just one more
reason to use ModelSim.
 
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Al Muliman
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      02-14-2009
On 14-02-2009 08:53, Al Muliman wrote:
> If this is an undocumented feature then I suppose it is just one more
> reason to use ModelSim.


For the sake of completeness, states containing "Z" also receive special
treament. States containing "U" or "X" gets one color, and states
containing "Z" gets another.
 
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Nicolas Matringe
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      02-14-2009
Al Muliman a écrit :
> On 14-02-2009 08:53, Al Muliman wrote:
>> If this is an undocumented feature then I suppose it is just one more
>> reason to use ModelSim.

>
> For the sake of completeness, states containing "Z" also receive special
> treament. States containing "U" or "X" gets one color, and states
> containing "Z" gets another.


So what if the name contains both Z and X (or U)? Just curious...

I suppose H, W and L also receive a special treatment. This is a really
stupid bug.

Nicolas
 
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Al Muliman
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      02-14-2009
On 14-02-2009 14:51, Nicolas Matringe wrote:
> So what if the name contains both Z and X (or U)? Just curious...


X and U beat Z

> I suppose H, W and L also receive a special treatment.


Not that I can tell.
 
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Al Muliman
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      02-14-2009
On 14-02-2009 14:56, Brian Drummond wrote:

> Can you create a simple example and submit a Webcase?


Example created, webcase access pending.

------------------------ Here's the example: ----------------------

library ieee;
use ieee.std_logic_1164.all;

entity colors is
port ( reset : in std_logic; clock : in std_logic );
end colors;

architecture behavioral of colors is
type state_type is (SZTATE1, STUATE2, SXTATE3, SZXTATE4, SZTUATE5,
SXTUATE6, STLATE7, STWATE8, STHATE9);
shared variable state : state_type;
begin
process(clock, reset)
begin
if (reset = '1') then
state := SZTATE1;
elsif rising_edge(clock) then
case (state) is
when SZTATE1 => state := STUATE2;
when STUATE2 => state := SXTATE3;
when SXTATE3 => state := SZXTATE4;
when SZXTATE4 => state := SZTUATE5;
when SZTUATE5 => state := SXTUATE6;
when SXTUATE6 => state := STLATE7;
when STLATE7 => state := STWATE8;
when STWATE8 => state := STHATE9;
when others => state := SZTATE1;
end case;
end if;
end process;
end behavioral;

---------------------- And the test bench: --------------------------

library ieee;
use ieee.std_logic_1164.all;

ENTITY colors_test_bench IS
END colors_test_bench;

ARCHITECTURE behavior OF colors_test_bench IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT colors
PORT(
reset : IN std_logic;
clock : IN std_logic
);
END COMPONENT;


--Inputs
signal reset : std_logic := '1';
signal clock : std_logic := '0';

-- Clock period definitions
constant clock_period : time := 1us;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: colors PORT MAP (
reset => reset,
clock => clock
);

-- Clock process definitions
clock_process rocess
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;


-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100ms.
-- wait for 100ms;

wait for clock_period*2;

-- insert stimulus here
reset <= '0';

wait;
end process;

END;
 
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Ken Cecka
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      02-14-2009
Al Muliman wrote:

> On 14-02-2009 14:56, Brian Drummond wrote:
>
>> Can you create a simple example and submit a Webcase?

>
> Example created, webcase access pending.


Thanks for the confirmation. I'll submit a webcase as well if you don't get a positive response to yours.

Ken

>
> ------------------------ Here's the example: ----------------------
>
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity colors is
> port ( reset : in std_logic; clock : in std_logic );
> end colors;
>
> architecture behavioral of colors is
> type state_type is (SZTATE1, STUATE2, SXTATE3, SZXTATE4, SZTUATE5,
> SXTUATE6, STLATE7, STWATE8, STHATE9);
> shared variable state : state_type;
> begin
> process(clock, reset)
> begin
> if (reset = '1') then
> state := SZTATE1;
> elsif rising_edge(clock) then
> case (state) is
> when SZTATE1 => state := STUATE2;
> when STUATE2 => state := SXTATE3;
> when SXTATE3 => state := SZXTATE4;
> when SZXTATE4 => state := SZTUATE5;
> when SZTUATE5 => state := SXTUATE6;
> when SXTUATE6 => state := STLATE7;
> when STLATE7 => state := STWATE8;
> when STWATE8 => state := STHATE9;
> when others => state := SZTATE1;
> end case;
> end if;
> end process;
> end behavioral;
>
> ---------------------- And the test bench: --------------------------
>
> library ieee;
> use ieee.std_logic_1164.all;
>
> ENTITY colors_test_bench IS
> END colors_test_bench;
>
> ARCHITECTURE behavior OF colors_test_bench IS
>
> -- Component Declaration for the Unit Under Test (UUT)
>
> COMPONENT colors
> PORT(
> reset : IN std_logic;
> clock : IN std_logic
> );
> END COMPONENT;
>
>
> --Inputs
> signal reset : std_logic := '1';
> signal clock : std_logic := '0';
>
> -- Clock period definitions
> constant clock_period : time := 1us;
>
> BEGIN
>
> -- Instantiate the Unit Under Test (UUT)
> uut: colors PORT MAP (
> reset => reset,
> clock => clock
> );
>
> -- Clock process definitions
> clock_process rocess
> begin
> clock <= '0';
> wait for clock_period/2;
> clock <= '1';
> wait for clock_period/2;
> end process;
>
>
> -- Stimulus process
> stim_proc: process
> begin
> -- hold reset state for 100ms.
> -- wait for 100ms;
>
> wait for clock_period*2;
>
> -- insert stimulus here
> reset <= '0';
>
> wait;
> end process;
>
> END;


 
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Dave Higton
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      02-14-2009
In message <resll.181$(E-Mail Removed)>
Ken Cecka <(E-Mail Removed)> wrote:

> I just spent all afternoon trying to figure out why isimwave (the xilinx
> simluation waveform viewer) was drawing my state machine value in red for
> certain states.
>
> I believe I've finally tracked it down: if my state name contains the
> letter 'X', xilinx draws it in red. For example, with the following
> states:
>
> TYPE state_type IS ( STATE1, STATE2X );
>
> Any time a signal has the value STATE1, it will be drawn in green. If it
> has the value STATE2X, it will be drawn in red.
>
> Posting this partly to see if others can confirm this behavior and/or give
> a better explanation, and partly to get it documented somewhere for the
> next poor soul who wonders what's causing there state machine to go into an
> invalid state.
>
> Also, I'm guessing this should be considered a bug in isimwave - is there
> anything in the language specification that says you can't use the letter X
> in your enumerated state names?


Widening the topic somewhat: isim is, by a country mile, the buggiest
software I use. I have a case in at the moment reporting two bugs (I
originally reported one, then another one came along...)

I find that, if I have a lot of signals in the simulation window, the
first simulation run after an edit of any of the source files causes
the simulation window to be only partly drawn. I have to close it and
re-run to get a fully drawn window. Also, infuriatingly, it will from
time to time randomly alter the order of signals in the simulation
window.

However, I find it dramatically faster than ModelSim.

A new version is expected to be released around April.

Dave

 
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