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VHDL - Re: Multiple instances

 
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Old 02-13-2009, 11:10 PM   #1
Default Re: Multiple instances



"mattia" <> wrote in message
news:4995fbd3$0$1110$. ..
> Hi all, I need some help. Which is the best way to instantiate multiple
> cores using the minimun additional logic available?


Instantiate each core and connect them with wires.

> Can you provide me
> some code?
>


entity Things is port(
Gazinta: in std_ulogic;
Gazouta: in std_ulogic);
end Things;
architecture RTL of Things is
signal bbb: std_ulogic;
begin
The_Thing1 : entity Thing1
port map(
a=> Gazinta,
b=> bbb);

The_Thing2 : entity Thing2
port map(
a=> bbb,
b=> Gazouta);
end RTL;

See, it's not that hard. Enjoy.

Kevin Jennings




KJ
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Old 02-14-2009, 12:35 AM   #2
KJ
 
Posts: n/a
Default Re: Multiple instances

"mattia" <> wrote in message
news:49960724$0$1112$. ..
> Il Fri, 13 Feb 2009 18:10:38 -0500, KJ ha scritto:
>
>> "mattia" <> wrote in message
>> news:4995fbd3$0$1110$. ..
>>> Hi all, I need some help. Which is the best way to instantiate multiple

<snip>
>
> Ok, but what if I want to feed all my instances with the same clock event
> so that executing one or N instances don't affect my performances?


You don't connect 'clock events', you connect signals. If you have multiple
instances that all need to be receiving some signal that happens to be named
'clock', then you simply put that signal name on the right side of the port
map

The_Thing1 : entity work.Thing1
port map(
a=> Gazinta,
x=> clock,
b=> bbb);

The_Thing2 : entity work.Thing2
port map(
a=> bbb,
y=> clock,
b=> Gazouta);

> I want
> to test the performances of a core instantiated multiple times in order
> to see if my device scale proportionally.


Is there something holding you back from doing just that? The example
entities 'Thing1' and 'Thing2' could just as easily be the same entity. For
example...
The_Thing1 : entity work.Thing1 port map(....);
The_Thing2 : entity work.Thing1 port map(....);

KJ




KJ
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