Velocity Reviews > VHDL > Re: division of two 4-bit vectors

Re: division of two 4-bit vectors

Benjamin Couillard
Guest
Posts: n/a

 02-13-2009
On 12 fév, 05:09, Jonathan Bromley <(E-Mail Removed)>
wrote:
> On Wed, 11 Feb 2009 15:02:31 -0800, My Name wrote:
>
> >I am sorry, i did not look for this topic on this forum, but i need
> >help, i am suposed to program a simple calculator in vhdl, and program
> >it on spartan 3 FPGA board... My assingment is to make a simple
> >calculator, i need to enter a two numbers (that are a 4 bit vectors) and
> >then enter a operand ( +, -, * or /). on my vhdl code everything is
> >working except division ( / ). and i dont know how to divide a two 4-bit
> >vectors..... please can anybody can help me... sorry for my bad
> >english.....

>
> For such tiny numbers, you could do "kindergarten division":
> repeatedly subtract the divisor from the dividend, counting
> how many times you do the subtraction, until the subtraction
> would give a negative result. *This could even be done
> as a purely combinational function - it would create truly
> horrible hardware, but it would work:
>
> * signal dividend, divisor, quotient, remainder:
> * * * * * * * * * * * * * * * * * *unsigned(3 downto 0);
> * .....
> * process (dividend, divisor)
> * * variable v: unsigned(3 downto 0);
> * * variable done: boolean;
> * begin
> * * v := dividend;
> * * done := false;
> * * for i in 0 to 15 loop
> * * * if not done then
> * * * * if v < divisor then
> * * * * * quotient <= to_unsigned(i, 4);
> * * * * * remainder <= v;
> * * * * * done := true;
> * * * * else
> * * * * * v := v - divisor;
> * * * * end if;
> * * * end if;
> * * end loop;
> * end process;
>
> For extra credit, explain why I used a "done" flag
> and a "for" loop, instead of a "while" loop.
>
> for anything serious.....? *And please promise that
> you will say something in your assignment report
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> (E-Mail Removed)://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

You have used the for loop because the number of iterations must be a
constant.
The done flag is used to stop the calculations when we're done because
if we only need 3 iterations, we don't need to calculate anything in
the last 13 iterations.

Is that it?

Benjamin Couillard
Guest
Posts: n/a

 02-13-2009
On 13 fév, 10:59, Benjamin Couillard <(E-Mail Removed)>
wrote:
> On 12 fév, 05:09, Jonathan Bromley <(E-Mail Removed)>
> wrote:
>
>
>
> > On Wed, 11 Feb 2009 15:02:31 -0800, My Name wrote:

>
> > >I am sorry, i did not look for this topic on this forum, but i need
> > >help, i am suposed to program a simple calculator in vhdl, and program
> > >it on spartan 3 FPGA board... My assingment is to make a simple
> > >calculator, i need to enter a two numbers (that are a 4 bit vectors) and
> > >then enter a operand ( +, -, * or /). on my vhdl code everything is
> > >working except division ( / ). and i dont know how to divide a two 4-bit
> > >vectors..... please can anybody can help me... sorry for my bad
> > >english.....

>
> > For such tiny numbers, you could do "kindergarten division":
> > repeatedly subtract the divisor from the dividend, counting
> > how many times you do the subtraction, until the subtraction
> > would give a negative result. *This could even be done
> > as a purely combinational function - it would create truly
> > horrible hardware, but it would work:

>
> > * signal dividend, divisor, quotient, remainder:
> > * * * * * * * * * * * * * * * * * *unsigned(3 downto 0);
> > * .....
> > * process (dividend, divisor)
> > * * variable v: unsigned(3 downto 0);
> > * * variable done: boolean;
> > * begin
> > * * v := dividend;
> > * * done := false;
> > * * for i in 0 to 15 loop
> > * * * if not done then
> > * * * * if v < divisor then
> > * * * * * quotient <= to_unsigned(i, 4);
> > * * * * * remainder <= v;
> > * * * * * done := true;
> > * * * * else
> > * * * * * v := v - divisor;
> > * * * * end if;
> > * * * end if;
> > * * end loop;
> > * end process;

>
> > For extra credit, explain why I used a "done" flag
> > and a "for" loop, instead of a "while" loop.

>
> > for anything serious.....? *And please promise that
> > you will say something in your assignment report
> > about division by zero?
> > --
> > Jonathan Bromley, Consultant

>
> > DOULOS - Developing Design Know-how
> > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

>
> > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> > (E-Mail Removed)://www.MYCOMPANY.com

>
> > The contents of this message may contain personal views which
> > are not the views of Doulos Ltd., unless specifically stated.

>
> You have used the for loop because the number of iterations must be a
> constant.
> The done flag is used to stop the calculations when we're done because
> if we only need 3 iterations, we don't need to calculate anything in
> the last 13 iterations.
>
> Is that it?

The number of iterations in a loop must be a constant for synthesis
IIRC.

Andy
Guest
Posts: n/a

 02-13-2009
On Feb 13, 10:03*am, Benjamin Couillard <(E-Mail Removed)>
wrote:
> On 13 fév, 10:59, Benjamin Couillard <(E-Mail Removed)>
> wrote:
>
>
>
>
>
> > On 12 fév, 05:09, Jonathan Bromley <(E-Mail Removed)>
> > wrote:

>
> > > On Wed, 11 Feb 2009 15:02:31 -0800, My Name wrote:

>
> > > >I am sorry, i did not look for this topic on this forum, but i need
> > > >help, i am suposed to program a simple calculator in vhdl, and program
> > > >it on spartan 3 FPGA board... My assingment is to make a simple
> > > >calculator, i need to enter a two numbers (that are a 4 bit vectors) and
> > > >then enter a operand ( +, -, * or /). on my vhdl code everything is
> > > >working except division ( / ). and i dont know how to divide a two 4-bit
> > > >vectors..... please can anybody can help me... sorry for my bad
> > > >english.....

>
> > > For such tiny numbers, you could do "kindergarten division":
> > > repeatedly subtract the divisor from the dividend, counting
> > > how many times you do the subtraction, until the subtraction
> > > would give a negative result. *This could even be done
> > > as a purely combinational function - it would create truly
> > > horrible hardware, but it would work:

>
> > > * signal dividend, divisor, quotient, remainder:
> > > * * * * * * * * * * * * * * * * * *unsigned(3 downto 0);
> > > * .....
> > > * process (dividend, divisor)
> > > * * variable v: unsigned(3 downto 0);
> > > * * variable done: boolean;
> > > * begin
> > > * * v := dividend;
> > > * * done := false;
> > > * * for i in 0 to 15 loop
> > > * * * if not done then
> > > * * * * if v < divisor then
> > > * * * * * quotient <= to_unsigned(i, 4);
> > > * * * * * remainder <= v;
> > > * * * * * done := true;
> > > * * * * else
> > > * * * * * v := v - divisor;
> > > * * * * end if;
> > > * * * end if;
> > > * * end loop;
> > > * end process;

>
> > > For extra credit, explain why I used a "done" flag
> > > and a "for" loop, instead of a "while" loop.

>
> > > Please, please promise you won't try to use that
> > > for anything serious.....? *And please promise that
> > > you will say something in your assignment report
> > > about division by zero?
> > > --
> > > Jonathan Bromley, Consultant

>
> > > DOULOS - Developing Design Know-how
> > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

>
> > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> > > (E-Mail Removed)://www.MYCOMPANY.com

>
> > > The contents of this message may contain personal views which
> > > are not the views of Doulos Ltd., unless specifically stated.

>
> > You have used the for loop because the number of iterations must be a
> > constant.
> > The done flag is used to stop the calculations when we're done because
> > if we only need 3 iterations, we don't need to calculate anything in
> > the last 13 iterations.

>
> > Is that it?

>
> The number of iterations in a loop must be a constant for synthesis
> IIRC.- Hide quoted text -
>
> - Show quoted text -

Most synthesis tools require "static" (from a synthesis POV) loop
bounds, which may or may not be constants. For instance, because for-
loops are unrolled for synthesis, the loop index becomes static, which
means that the loop index can form the bounds of an inner loop.

You can use an exit statement, executed under a static or dynamic
condition, to modify the loop iteration boundaries too.

Andy