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Problem with clock

aimendj aimendj is offline
Junior Member
Join Date: Feb 2009
Posts: 4

I'm working VHDL project. the problem is that the FPGA Frequency is not sufficient (Delay problem) so the solution is either:
-3 Prallel instrunction for each clock edge ==> complexity*3
-divide the clock by 3 ==> same complexity.

i think that the second solution is better but the problem is this suitable for the FPGA and is there any limit when dividing the clock?

Thanks for Help,
ODCOM Technologies
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