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Assignment to output signal from internal signal not istantaneous

 
 
dibacco73 dibacco73 is offline
Junior Member
Join Date: Feb 2009
Posts: 1
 
      02-10-2009
I have the following code snippet:

entity driver is
port
(
clk_o : out std_logic
);
end driver;
--
architecture rtl of driver is
begin
signal i_clk : std_logic :='0';
i_clk <= NOT i_clk AFTER 100ns;
clk_o <= i_clk;

clk_o is delayed respect to i_clk, is this possible?

Thank you,
Antonio.
 
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joris joris is offline
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Join Date: Jan 2009
Posts: 152
 
      02-12-2009
Yes, clk_o is assigned a "delta" period of time after i_clk. It's by design of VHDL.
You can get around this by using a proces instead (making i_clk a variable instead of a signal)
 
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