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[twinkle]

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.poly_pack.all;

entity DeMUX is
port(clk, rst : in std_logic;
input : in std_logic_vector(INPUT_WIDTH-1 downto 0);
out1_dmux : out std_logic_vector(INPUT_WIDTH-1 downto 0);
out2_dmux : out std_logic_vector(INPUT_WIDTH-1 downto 0)
);
end DeMUX;

architecture behavior of DeMUX is
signal sel : std_logic;
begin

process(sel,input)
begin

case sel is
when '1'=>
out1_dmux <= input;
out2_dmux <= "00000000";

when '0' =>
out2_dmux <= input;
out1_dmux <= "00000000";

when others =>
out1_dmux <= "00000000";
out1_dmux <= "00000000";
end case;

end process;


process (clk, rst)
begin
if (rst = '0') THEN
sel <= '1';
else
if (clk'event and clk = '1')then
sel <= sel + 1;
end if;
end if;
end process;
end behavior;

I get the following two errors when am incrementing my 'sel'. i.e., the problem is shown in sel <= sel+1. Please some one help me in resolving this problem.

Errors shown:

No feasible entries for infix operator "+"
Type error resolving infix expression "+" as type ieee.std_logic_1164.std_logic

Thanking you!!


/Twinkle

[eliascm]

sel is type std_logic so "sel + 1" is not defined. You could use "sel <= not sel" to alternate the state of sel (you should first set sel to a default state of '1' or '0' since "not sel" will not work for the other possible states of sel.

[twinkle]

Yaa now I realize the mistake...Thank you very much!!