Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > help in VHDL procedure programming

Reply
Thread Tools

help in VHDL procedure programming

 
 
VIPS
Guest
Posts: n/a
 
      02-04-2009
Hi All

i am trying to write a procedure in VHDL which i want to generate
clock and on the rising edge of the clock i want to shift data on the
rising edge .

When i use the clause Rising_edge(clk) it is not doing anything and no
output is seen ..

Can anyone help as how to generate a clock inside the procedure and
then shift data on that clock.

I want the output of the procedure to give serial data on its
generated clock

Thanks in advance

Vipul
 
Reply With Quote
 
 
 
 
eliascm eliascm is offline
Member
Join Date: Jan 2009
Posts: 42
 
      02-05-2009
rising_edge(clk) does not generate a clock, but rather detects the rising edge of the signal "clk". An example of its use:

dff : process(clk)
begin
if rising_edge(clk) then
q <= d;
end if;
end process;

q and d are signals declared elswhere.

Creating a synthesizable clock signal in a process is not something I would recommend. The clock timing would be difficult to control. Typically, a clock signal is generated by an external crystal oscillator.

Generating a clock signal for simulation is another matter.


clk_gen: process
begin
if not end_sim then
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
else
wait;
end if;
end process;

The reason for using the boolean signal end_sim is to stop the clk_gen process when the simulation is ended; otherwise the process will keep running and the simulation will not end;

I hope this helps.
 
Reply With Quote
 
 
 
 
Enes Erdin
Guest
Posts: n/a
 
      02-05-2009
On 4 Šubat, 14:23, VIPS <(E-Mail Removed)> wrote:
> Hi All
>
> i am trying to write a procedure in VHDL which i want to generate
> clock and on the rising edge of the clock i want to shift data on the
> rising edge .
>
> When i use the clause Rising_edge(clk) it is not doing anything and no
> output is seen ..
>
> Can anyone help as how to generate a clock inside the procedure and
> then shift data on that clock.
>
> I want the output of the procedure to give serial data on its
> generated clock
>
> Thanks in advance
>
> Vipul


Hi,

You have to indicate for which purpose you will use this procedure.
For testbench or for synthesis.

For synthesis you can not generate clocks internally as you think. You
must connect a clock pin or again generate a clock from a PLL by
connecting a "real" clock.

--enes
 
Reply With Quote
 
Mike Treseler
Guest
Posts: n/a
 
      02-05-2009
VIPS wrote:

> i am trying to write a procedure in VHDL which i want to generate
> clock and on the rising edge of the clock i want to shift data on the
> rising edge .


If I want to drive a port or signal, I need
an architecture containing a parallel statement or a process.
A process contains one or more sequential statements.

A procedure could be called by this process to
provide sequential statements, but a procedure
alone cannot drive a port or signal.

For a related example, see the process tb_clk here:
http://mysite.verizon.net/miketreseler/test_uart.vhd
Notice that this process calls the procedure fixed_stim
to supply supply sequential statements for counting
and stimulus generation.

-- Mike Treseler
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
procedure as argument in procedure AlexWare VHDL 2 10-23-2009 09:14 AM
Procedure VHDL hilal VHDL 3 09-03-2008 08:47 AM
VHDL-2002 vs VHDL-93 vs VHDL-87? afd VHDL 1 03-23-2007 09:33 AM
'Procedure or function <stored procedure name> has too many arguments specified',,,ARGH! Mike P ASP .Net 0 06-19-2006 01:19 PM
How to specify default value to a variable of unconstrained type INSIDE a VHDL procedure ? Pankaj VHDL 2 08-23-2004 04:36 AM



Advertisments