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Automating VHDL Simulations in ModelSim

 
 
Georg
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      02-03-2009
Tricky wrote:
>
> Why not just use a generate loop to instantiate the DUTs and processes
> X times (in parrallel), that dump out to X log files?
>
> entity my_tb is
> generic (
> generic_list : int_array := (0, 1, 2, 3, 4);
> );
> end entity my_TB
>
> ...
>
> test_gens : for i in generic_list'range generate
>
> DUT : my_ent
> generic map (
> foo => generic_list(i);
> );
>
> process
> file my_log : text open WRITE_MODE is
> ( "logfile" & integer'image(generic_list(i)) & ".log");
> begin
> ....
> end process;
>
> end generate test_gens;
>


Ah, I see, that looks clever. Well, IMO that's still a structural
testbench (if I understood the meaning of 'structural' right), but it
should do what I need. I'll try it out later, right now I'm taking
advantage of Jonathan's hint.

Thanks to you and all others who have replied!
Georg
 
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petrovski101@gmail.com
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      02-03-2009
I wrote a tcl/tk GUI that parses the top level entity and outputs a
generic vhdl testbench. The testbench creates a clock to read data
from a synchronous textio process. A counter is loaded with the most
significant 16 bits of this array of data. This counter determines
how long to sit at each test vector. The remaining bits of the array
are stimulus.

The top level code is usually a collection of bus functional models,
address mapped to my textio stimulus, and the unit under test.

A seperate TCL program generates the test vectors and outputs expected
results. The testbench outputs it's results to a file and a bash
script compares the two. You can generate constrained random test
vectors this way in the tcl script as part of regression test.

Although textio is slow to simulate, I find it's generally fast enough
for my needs.

Pete
 
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Jan Decaluwe
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      02-03-2009
http://www.velocityreviews.com/forums/(E-Mail Removed) wrote:
> I wrote a tcl/tk GUI that parses the top level entity and outputs a
> generic vhdl testbench. The testbench creates a clock to read data
> from a synchronous textio process. A counter is loaded with the most
> significant 16 bits of this array of data. This counter determines
> how long to sit at each test vector. The remaining bits of the array
> are stimulus.
>
> The top level code is usually a collection of bus functional models,
> address mapped to my textio stimulus, and the unit under test.
>
> A seperate TCL program generates the test vectors and outputs expected
> results. The testbench outputs it's results to a file and a bash
> script compares the two. You can generate constrained random test
> vectors this way in the tcl script as part of regression test.
>
> Although textio is slow to simulate, I find it's generally fast enough
> for my needs.
>
> Pete


Can't resist, sorry

http://www.myhdl.org/doku.php/why#yo...he_design_flow

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a hardware description language:
http://www.myhdl.org
 
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petrovski101@gmail.com
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      02-03-2009
On Feb 3, 10:08*am, Jan Decaluwe <(E-Mail Removed)> wrote:
> (E-Mail Removed) wrote:
> > I wrote a tcl/tk GUI that parses the top level entity and outputs a
> > generic vhdl testbench. *The testbench creates a clock to read data
> > from a synchronous textio process. *A counter is loaded with the most
> > significant 16 bits of this array of data. *This counter determines
> > how long to sit at each test vector. *The remaining bits of the array
> > are stimulus.

>
> > The top level code is usually a collection of bus functional models,
> > address mapped to my textio stimulus, and the unit under test.

>
> > A seperate TCL program generates the test vectors and outputs expected
> > results. *The testbench outputs it's results to a file and a bash
> > script compares the two. *You can generate constrained random test
> > vectors this way in the tcl script as part of regression test.

>
> > Although textio is slow to simulate, I find it's generally fast enough
> > for my needs.

>
> > Pete

>
> Can't resist, sorry
>
> http://www.myhdl.org/doku.php/why#yo...guages_intensi...
>
> --
> Jan Decaluwe - Resources bvba -http://www.jandecaluwe.com
> * * *Python as a hardware description language:
> * * *http://www.myhdl.org- Hide quoted text -
>
> - Show quoted text -


That's quite interesting. I considered something similar in the past
but decided not to take the plunge. Instead, I wanted a generic
interface that could be driven by programs other than tcl. My
testbenches are written in tcl but the output vectors are just a
string of ascii 1's and 0's. You could just as easily create testbench
stimulus with C, Perl, Python... whatever.

I'm also leaning less towards generic language and more towards
generic templates. I have templates to generate register files and
state machines. I like to describe the more common elements of a
design in as few lines of code as possible (because I'm lazy). The
templates also generate groff code for documentation. Register file =
table, State Machine = state diagram + equations. Change the template
and both vhdl and groff code gets updated. These get imported into my
chip documentation automatically. Docs are created as you go rather
than at the end of the project, when you're forgotten half the
details.

I do like your simulator. That's slick.
 
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