verilog code errorneous

funkyrobot · 01-31-2009

I've got a problem with my Verilog code. The 'always' construct should re-run when either RecButtons, FloorNr or Direction has changed. Still, it runs only once when RecButtons has changed. Can you find a conceptual error here?

-Siim

It doesn't have to be synthetizable

Code:

always
begin
   $display("Starting elevator control function (time %d)", $time);
   if(AutoReset == 1)
   begin
      FloorNr = 0;
      Direction = right;
      RunMotors = 0;
      for(j = 0; j < NUM_FLOORS; j = j + 1)
      begin
         ReleaseButtons[j] = 0;
         DoorsOpen[j] = 0; 
      end
   end
   else
   begin
      if(RecButtons[FloorNr] == 1)
      begin
         DoorsOpen[FloorNr] = 1;
         ReleaseButtons[FloorNr] = 1;
         #50
         ReleaseButtons[FloorNr] = 0;
         DoorsOpen[FloorNr] = 0; 
      end
      if(ButtonsDir == 1)
      begin
         RunMotors = 1;
         #10
         RunMotors = 0;
         if(   Direction[0] == right[0] &&
               Direction[1] == right[1])
            FloorNr = FloorNr + 1;
         else
         if(   Direction[0] == left[0] &&
               Direction[1] == left[1])
            FloorNr = FloorNr - 1;
      end
      else
      begin
         if(ButtonsOtherDir == 1)
         begin
            Direction = OtherDir;
            RunMotors = 1;
            #10
            RunMotors = 0;
            if(   Direction[0] == right[0] &&
                  Direction[1] == right[1])
               FloorNr = FloorNr + 1;
            else
            if(   Direction[0] == left[0] &&
                  Direction[1] == left[1])
               FloorNr = FloorNr - 1;
         end
      end
   end
   @(RecButtons, FloorNr, Direction);
   //@(AutoReset, RecButtons, FloorNr, DoorsOpen, ReleaseButtons,
   //         ButtonsDir, RunMotors, Direction, ButtonsOtherDir, OtherDir);
end

funkyrobot · 02-03-2009

Actually the problem is using "#"-delays in this behavioral model. Does anyone have an idea how to add the delays without using an external clock signal. Any help or comments appreciated!

Similar Threads
Thread	Thread Starter	Forum	Replies	Last Post
Verilog Code to VHDL Code	pplnet	VHDL	0	12-09-2009 04:18 PM
Verilog Code	dcell	VHDL	1	11-21-2004 01:21 PM
VHDL/Verilog code for DMA Controller	lovely	VHDL	1	04-12-2004 04:30 PM
Re: How to convert VHDL/ verilog code to layout?	Poly Diffusion	VHDL	2	02-09-2004 05:00 PM
where to find DCT/IDCT for JPEG/JPEG2000 VHDL/VERILOG source code?	walala	VHDL	0	08-01-2003 09:44 PM