To infer a ram lut based:
Each Slice have two Logic Cell and each logic cell have a LUT (SRAM 16 word x 1 bit)
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LUT_RAM is
port(wr_en,clk: in std_logic;
addr: in std_logic_vector(4 downto 0);
di: in std_logic;
do: out std_logic);
end LUT_RAM;
architecture Behave of LUT_RAM is
type bit_array is array(0 to 15) of std_logic;
signal RAM_0: bit_array;
begin
process(clk)
begin
if rising_edge(clk) then
if wr_en='1' then
RAM_0(conv_integer(unsigned(addr)))<=di;
end if;
end if;
end process;
do<=RAM(conv_integer(unsigned(addr)));
end Behave;
Depending on RAM size you want. Change
Code:
addr: in std_logic_vector(4 downto 0);
di: in std_logic -> std_logic_vector ...;
do: out std_logic-> std_logic_vector ...
and
Code:
type bit_array is array(0 to 16) of std_logic; -> type bit_array is array(0 to Size-1) of std_logic_vector ...;
if you want to precharge the RAM:
Code:
signal RAM_0: bit_array:=('0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0');
Here is the Code that I'm using for a quad port ram with write and read address independents using blockRAM.
Here is the link to the code "
www
.velocityreviews
.com/forums/t665498-quad-port-ram.htm"
Similar Threads
