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Re: sw guy question about latches

 
 
Andy
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      01-20-2009
On Jan 18, 11:04*pm, Mike Treseler <(E-Mail Removed)> wrote:
> d p chang wrote:
> > i'm a sw guy wandering through teaching myself a little bit about
> > (digital) hw, and want to try to go about this 'idiomatically' rather
> > than trying to translate my sw thinking into hdl (and coming up w/ crap
> > hdl).

>
> Match a synchronous template.
> That will simplify synthesis.
> I recommend single process entities to
> the sequentially inclined.
>
> Details:http://mysite.verizon.net/miketreseler/


Mike has given you good advice. I would also add that a single,
clocked process will not give you latches, regardless of whether a
signal or variable is updated on that clock cycle. If one is not
updated, a clock enabled register is inferred, with appropriate
circuit to drive the enable input.

BTW, "Z" is not synonymous with "don't care," it is a tri-state (high
impedance) value used "turn off" a driver on busses with more than one
driver. If your target hardware does not support a tri-state bus
internally, the synthesis tool will convert tri-state busses to
multiplexers for you (probably not what you intended in this case).
"Don't care" is usually specified as either 'X' or '-'.

Andy
 
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Tricky
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      01-22-2009
A clock enablled register uses the following VHDL template:

process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
--do stuff
end if;
end if;
end process;

What you have built by removing the defaults is NOT registers - but
latches. The 2 process state machine process requires that all signals
in the process be assigned a value for EVERY possible case. The
defaults are there as default conditions, and so will always assign a
value unless specified.

The easiest way to avoid this is to move the whole state machine into
a single process, then you CANNOT infer transparent latches.
 
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