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On Jan 20, 12:19*pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> * q <= '0' when rst = '1' else FUNC(d,q) when rising_edge(clk);

Yep, that'll work, assuming q is not an output port.

This is one of those interesting situations where the RTL (in a
process) can describe a behavior without having to read an output, but
the implementation must read the output, or a buffered version thereof
(clock enables are usually done with a multiplexer on the register
input, with one of the mux inputs being the register's output).

Andy

On Jan 21, 12:27*pm, Jim Lewis <j...@synthworks.com> wrote:

> I don't find asynchronous and synchronous reset trade-off as clear
> cut as this. *Does anyone else have a compiled summary of the
> whys and why nots of asynchronous vs synchronous resets?
>
> Off the top of my head, this is what I consider:
> Match what the target technology (FPGA or ASIC) does best.
> * *If the technology natively supports asynchronous resets, synchronous
> * *reset will cost you a data path element or part of one in an FPGA (one
> * *input in a LUT based FPGA). *In some cases this will increase both
> * *area and timing.
>

--snip--

I've seen both utilization and timing improve somewhat in Xilinx
Virtex-4 designs when switching from async to synchronous resets. I'm
led to believe this is because the sync reset inputs of the flops can
be used to implement some of the synchronous logic as well, giving the
synthesizer new optimization opportunities. Synchronous logic
obviously can't be optimized into an async reset input of a flop.

Dave