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When did global signals become part of VHDL

 
 
Brian Davis
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      01-18-2009
Dave wrote:
>
> I like the idea of synthesizing global signals for test port
> connections. We use the free version of ISE and Modelsim XE, and don't
> have access to SignalSpy or ChipScope.
>


Note that XST's support of globals in synthesis is very
limited, so this won't work as an in circuit probe.

There was a thread about this over on comp.arch.fpga
last fall, summary post here:
http://groups.google.com/group/comp....f20575a54da960

Brian
 
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Tricky
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      01-19-2009
On 18 Jan, 14:52, Brian Davis <(E-Mail Removed)> wrote:
> Dave wrote:
>
> > I like the idea of synthesizing global signals for test port
> > connections. We use the free version of ISE and Modelsim XE, and don't
> > have access to SignalSpy or ChipScope.

>
> *Note that XST's support of globals in synthesis is very
> limited, so this won't work as an in circuit probe.
>
> *There was a thread about this over on comp.arch.fpga
> last fall, summary post here:http://groups.google.com/group/comp....f20575a54da960
>
> Brian


Had a reply from Altera that basically on the lines of Brian
Drummond's post. They will not support it and do not recommend coding
in this way.
 
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