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aggregate assignments

 
 
ed.agunos@gmail.com
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      01-09-2009
we can do stuff like this:

signal some_signal : std_logic_vector(15 downto 0);

some_signal <= (15 downto 12 => '1', others => '0');

BUT.... is there someway we can do something like this:

some_signal <= (15 downto 12 => "1010", others => '0');

Thanks in advance
 
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Dave
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      01-10-2009
On Jan 9, 6:57*pm, (E-Mail Removed) wrote:
> we can do stuff like this:
>
> * * signal some_signal : std_logic_vector(15 downto 0);
>
> * * some_signal <= (15 downto 12 => '1', others => '0');
>
> BUT.... is there someway we can do something like this:
>
> * * some_signal <= (15 downto 12 => "1010", others => '0');
>
> Thanks in advance


How about:

some_signal <= (others => '0');
some_signal(15 downto 12) <= "1010";

Dave
 
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uhu01 uhu01 is offline
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Join Date: Jan 2009
Posts: 1
 
      01-10-2009
Hi,

I'm not a VHDL Pro, but the first thing that comes to my mind is something like:

constant zeroes : std_logic_vector(11 downto 0) := "00000000000";
some_signal <= "1010" & zeroes;

Regards,
Andreas
 
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