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multiple constant drivers for net IOP_

 
 
jasonkee111 jasonkee111 is offline
Junior Member
Join Date: Dec 2008
Posts: 5
 
      12-29-2008
IOP_ALU consists of 2 module: IOP and ALU(DUT). the inputpin mentioned(confused) is the input to DUT which is the output of the IOP as you can view in the attachment.

I have the errors as mentioned in the title by compiling it.
This is the code as below:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity IOP_ALU is
generic (
m: integer := 28;
n: integer := 8
);
port (
-- Enter port list here
clk_25mhz : in std_logic;
reset_b : in std_logic;
serial_in : in std_logic;
serial_out : out std_logic
);
end IOP_ALU;

architecture IOP_ALU_arch of IOP_ALU is

signal ack, busy : std_logic;
signal inputpin : std_logic_vector(m-1 downto 0);
signal outputpin : std_logic_vector(n-1 downto 0);

signal selop : std_logic_vector(3 downto 0);
signal R0 : std_logic_vector (7 downto 0);
signal A : std_logic_vector(7 downto 0);
signal B : std_logic_vector(7 downto 0);
signal alu_out : std_logic_vector(7 downto 0);
signal ccr : std_logic_vector(1 downto 0);

component ALU_2
port (
ccr : buffer STD_LOGIC_VECTOR(1 downto 0);-- ccr(1)-negative, ccr(0)-zero
R0 : in std_logic_vector(7 downto 0);
A : in STD_LOGIC_VECTOR(7 downto 0);
B : in STD_LOGIC_VECTOR(7 downto 0);
selop : in STD_LOGIC_VECTOR(3 downto 0);
-- ccr_out : out STD_LOGIC_VECTOR(2 downto 0);
alu_out : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;

component IOP
generic (
n: integer := n;
m: integer := m
);
port (
-- testing_cout_out : out std_logic_vector(7 downto 0);
reset_b : in STD_LOGIC;
serial_out : out std_logic;
serial_in : in std_logic;
-- error1 : out std_logic;
-- error2 : out std_logic;
clk_25mhz : in STD_LOGIC;
-- input_eq : out std_logic;
-- t_out_equal : out std_logic;
inputpin : buffer std_logic_vector(m-1 downto 0);
outputpin : in std_logic_vector(n-1 downto 0);
ack : out std_logic ;-- signal from to indicate continue CPU execution
busy : in std_logic -- signal to indicate transfer data
);
end component;

begin


inputpin <= selop & R0 & A & B;
outputpin <= alu_out;


-- VHDL Module Generator component instantiations
U_ALU_2: ALU_2
port map (ccr, R0, A, B, selop, alu_out);

U_IOP: IOP
port map (reset_b, serial_out, serial_in, clk_25mhz, inputpin, outputpin, ack, busy);

-- Enter concurrent statements here
end IOP_ALU_arch;

Thanks.
 
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