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Nested FOR loops in VHDL...

yokeshr

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Join Date: Dec 2008

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Posts: 1

12-16-2008

Hi people...

I designed a generic parallel CRC generator and i used nested for loops for tat...When simulated, there is no prob with this... But synthesis doesn't procede at all... Some said nested FOR loops sre not synthsizable... On googlin, I couldn find a constraint like tat... Can anyone help me wit this...

Thanks and Regards,
Yokesh

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