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A problem with conv_integer

 
 
ThWolf ThWolf is offline
Junior Member
Join Date: Dec 2008
Posts: 2
 
      12-13-2008
Hi

I want to write a simple demux, yet I wanted to make it as short as possible. Therefore I used conv_integer, but it showed me a strange error (I'm using quartus 6.0, and have tried the same program in ISE). The error makes somewhat sense, but I want to find a solution so that I don't have to use case (and be able to use a generic).
Here is the code:

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

Entity Demux is
port (I : in std_logic;
S: in std_logic_vector(2 downto 0);
Q: out std_logic_vector(7 downto 0));
End entity;

Architecture behave of Demux is
Begin
Process(S,I)
Begin
Q <= (conv_integer(unsigned(s)) => I, others => 'Z');
end process;
end architecture;

The error that shows up is:
Error (10318 ): VHDL aggregate error at demux.vhd(16): choice must be constant

Thank you for your help.
 
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jeppe jeppe is offline
Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 348
 
      12-14-2008
A wild quess - this code will work better

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

Entity Demux is
port (I : in std_logic;
S: in std_logic_vector(2 downto 0);
Q: out std_logic_vector(7 downto 0));
End entity;

Architecture behave of Demux is
Begin
Process(S,I)
Begin
Q <= (others => 'Z');
Q(conv_integer(unsigned(s))) <=I;
end process;
end architecture;

Jeppe
 
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ThWolf ThWolf is offline
Junior Member
Join Date: Dec 2008
Posts: 2
 
      12-15-2008
Yeah, it works, thats actually the first code I wrote, and it worked well in ISE (I didn't have quartus back then). Thing is, I wrote this code as homework, and when I tried to simulate it in class (we use MAX-plus2), it didn't worked. Furthermore, it showed a warning (not an error) - That there has been more then one assignment to Q, and only the last one will be taken into account.
 
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