Re: Xilinx VHDL coding styles,lookin for a tutorial

On 2 Dec, 17:33, "blisca" <bliscachiocciolinatiscalipuntoit> wrote:
> Hi
> I am lookin for information about good coding style when using Xilinx
> devices(Spartan 3 mostly),i mean templates for correct and efficient
> implementation of clock dividers,multiplexers,RAM and so on,so that the
> result could be easy to analyze and syntethize to the tool
>
> Many thanks
>
> Diego

For Ram, Muxes, registers (ie. basic fabric) its normally just best to
write clear generic code that could be read by any synthesisor,
they're pretty good at interpreting what you mean for the given
device. Just remember to simulate, simulate, simulate before you
actually try and put it on a chip. There isnt really any specific
Xilinx template for code, other than directly instatiating the library
primitives.

As for clock dividers, you'd best stick with the DCM entity and read
up in the data sheet as to how it works. Afaik, its not so feasible to
infer a digital clock divider in RTL VHDL.

Tricky

[jeppe]

Well - even I prefer a Spartan 3E kit could there be information at my site:
http://www.jjmk.dk/

Your welcome

jeppe