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Tesbench loop (Run through all address/data line combinations)

Daryl Daryl is offline
Junior Member
Join Date: Nov 2008
Posts: 2
I have asked a similar question allready on this forum but got no replies yet.
So I thought I think i should rephrase my question.

I have the following process inside a test bench (See below after dottted line).
Basically my VHDL code describes a Dual port RAM.
The test bench process:Writes data with C side and reads with L side, this seems to work.
But as you can imagine 2^5 Address line = 32 cominations * *-bit data = 512 bits memory locations.
My question is how can I optimize my testbench process so that It runs through all Address and data combinations????
Intead of making 512 different situations????

--C_SIDE write DATA:

C_ADDRESS <= "00001"; --Address
C_DATA_UB <= "00000000"; --Data upper byte
C_DATA_LB <= "00000000"; --Data lower byte
C_CS <= '0'; --Chip select
C_WE <= '0'; --Write enable
C_UBE <= '0'; --Upper byte enable
C_LBE <= '0'; --Lower byte enable
wait for 200 ns; --Write pulse length

--L_SIDE read DATA:

L_ADDRESS <= "00001"; --Address
L_CS <= '0'; --Chip select
L_OE <= '0'; --Output enable (Read)
wait for 200 ns; --Read pulse length

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