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VHDL - how to show a number in output text? |
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#1 |
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Hello group, I'm learning to write a testbench so in part of the code I increment a variable to count number of errors during simulation. now, I need to know how I can print out a message showing number of detected errors as following: Found n error(s). where n is the value in the counter variable. Any help is appreciated. p.s. I thought using & to concatenate would work but no report "Found " & err_cnt & " error(s)" !!!! (wrong) Amit |
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#2 |
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Posts: n/a
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On 30 ×*ובמבר, 14:30, Brian Drummond <brian_drumm...@btconnect.com>
wrote: > On Sun, 30 Nov 2008 02:21:04 -0800 (PST), Amit <amit.ko...@gmail.com> > wrote: > > > > >Hello group, > > >I'm learning to write a testbench so in part of the code I increment > >a variable to count number of errors during simulation. > >p.s. I thought using & to concatenate would work but no > > >report "Found " & err_cnt & " error(s)" Â* !!!! Â*(wrong) > > Concatenation works perfectly ... on strings, but err_cnt isn't a > string. > > What you need depends on the type of err_cnt. > If it is integer, simply > report "Found " & integer'image(err_cnt) Â*& " error(s)" > will do. > > - Brian Some examples (from an AHB monitor VHDL code) at h--p://bknpk.no-ip.biz/AHB_MON/ahb_mon_1.html You may also find this page intresting as well: http://bknpk.no-ip.biz/I2C/leon_2.html VHDL component to generate VCD waves to replace GHDL VCD wave dump option Pinhas |
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#3 |
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Posts: n/a
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On Nov 30, 5:44*pm, David Bishop <dbis...@vhdl.org> wrote:
> Amit wrote: > > Found n error(s). > > > where n is the value in the counter variable. > > > Any help is appreciated. > > > p.s. I thought using & to concatenate would work but no > > > report "Found " & err_cnt & " error(s)" * !!!! *(wrong) > > Currently what you have to do is (as others have noted): > report "Found " & integer'image(err_cnt) & " error(s)" > > IN VHDL-2008 (which some vendors are starting to look at) you can do this: > > report "Found " & to_string(err_cnt) & " error(s)" > > The "to_string" function is overloaded for EVERY type, so you can use it > on STD_LOGIC_VECTOR, UNSIGNED, Boolean, etc... Thanks to all for your comments and help. Regards, Amit Amit |
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