Problem with post-route simulation / timing simulation

Hi there, I tried to run my design using modelsim through Xilinx ISE, However it seems i keep encountering this problem. Can anyone know what isthe problem and how to fix this ? ... It seems to be missing a library named simprim. But I have no idea how to get the library and implement it ? ...

Help is appreciated thanks.

# -- Loading package standard
# -- Loading package std_logic_1164
# ** Error: (vcom-19) Failed to access library 'simprim' at "simprim".
# No such file or directory. (errno = ENOENT)
# ** Error: C:/FPGAdv71LSPS/Modeltech/win32/vcom failed.
# Error in macro ./tb_TopLevelRS232.tdo line 6
# C:/FPGAdv71LSPS/Modeltech/win32/vcom failed.
# while executing
# "vcom -explicit -93 "netgen/par/TopLevelRS232_timesim.vhd""

jasperng