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vhdl+signal inistilization problem

 
 
NIOS NIOS is offline
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      11-26-2008
hello,
iam actually working on a vhdl code that contains an FSM and i have a problem of initilization of one of the signals that iam using

iam using a process ,i initialized this signal

if(rst='1') then

signal name<=(others=>'0'));

but in the simulation this signal is XXXXXXXX when rst='1' and even after
 
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NIOS NIOS is offline
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      11-26-2008
the signal that i am talking about is an output not an internal signal
 
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