VHDL - Generation of 4.096MHz clock from 7.680MHz clock

11-24-2008, 06:30 AM

Hi friends,
In my design, I require an output clock 4.096MHz to be generated from 7.680MHz clock. I tried it but I am not getting acceptable output. Can anybody suggest something?

regards
pankaj

pankaj.goel

Ardni · 11-24-2008, 07:52 AM

Hi,
What type of FPGA are you using?
Have you thought about using a PLL to do this?

Ardni

jeppe · 11-24-2008, 10:34 AM

Well - it will "cost you" 4 DCM's in a XiLinx FPGA to multiply the frequency with 8:

With the new frequency 7.680 * 8 = 61.440 MHz can you get the wanted result by dividing with 15.

jeppe

pankaj.goel · 11-24-2008, 12:56 PM

Hi Ardni...thanks for showing interest...

I am using Altera cyclone II series FPGA for my design. The PLL doesn't support frequencies in the range of 4MHz and 7MHz. PLL works with 10MHz and above frequency. Try yourself.

pankaj

pankaj.goel

pankaj.goel · 11-24-2008, 01:00 PM

Hi Jeppe...thanks for the idea...I will try it using my altera cyclone II FPGA...

pankaj

pankaj.goel

Ardni · 11-24-2008, 01:13 PM

Hi,
Thats a pity, as it can be implemented using an enhanced PLL on other families. I have done this on stratix devices without problems. But as you say the fast PLL type is only supported on Cyclone II.

Anyway if I think of anything I´ll post it.

Ardni

pankaj.goel · 11-25-2008, 11:51 AM

Hi jeppe...In my cyclone II device, I am unable to multiply 7.68MHz frequency. PLL is not accepting 7.68MHz as input. I think minimum value it accept is 10MHz.
If you come across some solution, let me know.

thanks
pankaj

pankaj.goel

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11-24-2008, 06:30 AM	#1
	Generation of 4.096MHz clock from 7.680MHz clock Hi friends, In my design, I require an output clock 4.096MHz to be generated from 7.680MHz clock. I tried it but I am not getting acceptable output. Can anybody suggest something? regards pankaj pankaj.goel Last edited by pankaj.goel : 11-24-2008 at 06:32 AM.

11-24-2008, 07:52 AM	#2
Ardni Junior Member Join Date: Jul 2008 Posts: 24	Hi, What type of FPGA are you using? Have you thought about using a PLL to do this? Ardni

11-24-2008, 10:34 AM	#3
jeppe Senior Member Join Date: Mar 2008 Location: Denmark Posts: 245	Well - it will "cost you" 4 DCM's in a XiLinx FPGA to multiply the frequency with 8: With the new frequency 7.680 * 8 = 61.440 MHz can you get the wanted result by dividing with 15. jeppe

11-24-2008, 12:56 PM	#4
pankaj.goel Junior Member Join Date: Nov 2008 Posts: 8	Hi Ardni...thanks for showing interest... I am using Altera cyclone II series FPGA for my design. The PLL doesn't support frequencies in the range of 4MHz and 7MHz. PLL works with 10MHz and above frequency. Try yourself. pankaj pankaj.goel

11-24-2008, 01:00 PM	#5
pankaj.goel Junior Member Join Date: Nov 2008 Posts: 8	Hi Jeppe...thanks for the idea...I will try it using my altera cyclone II FPGA... pankaj pankaj.goel

11-24-2008, 01:13 PM	#6
Ardni Junior Member Join Date: Jul 2008 Posts: 24	Hi, Thats a pity, as it can be implemented using an enhanced PLL on other families. I have done this on stratix devices without problems. But as you say the fast PLL type is only supported on Cyclone II. Anyway if I think of anything I´ll post it. Ardni

11-25-2008, 11:51 AM	#7
pankaj.goel Junior Member Join Date: Nov 2008 Posts: 8	Hi jeppe...In my cyclone II device, I am unable to multiply 7.68MHz frequency. PLL is not accepting 7.68MHz as input. I think minimum value it accept is 10MHz. If you come across some solution, let me know. thanks pankaj pankaj.goel