VHDL - Clock Frequency & timming constraints

11-22-2008, 07:26 AM

Tool: Xilinx ISE 9.1

I'm doing a multiplier for binary number and i get a clock frequecncy value in synthesis report does this meaning thing? specially i assign other clock frequency in timing constraints.

samehsh

jeppe · 11-22-2008, 09:11 AM

I guess the value you got in the rapport would be the Max frequency - you can use lower frequencies in the real design

Jeppe

jeppe

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11-22-2008, 07:26 AM	#1
	Clock Frequency & timming constraints Tool: Xilinx ISE 9.1 I'm doing a multiplier for binary number and i get a clock frequecncy value in synthesis report does this meaning thing? specially i assign other clock frequency in timing constraints. samehsh

11-22-2008, 09:11 AM	#2
jeppe Senior Member Join Date: Mar 2008 Location: Denmark Posts: 245	I guess the value you got in the rapport would be the Max frequency - you can use lower frequencies in the real design Jeppe jeppe