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Writing std_logic_vector?

 
 
Philipp
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      11-21-2008
Hi

I am wondering if there is any way that I can write a
std_logic_vector(31 downto 0) into a file and there is should
be written then as a HEX value? Is there something like

val = ABC(31 downto 0);
write(s, hex'(val));

Thanks
 
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KJ
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      11-21-2008
On Nov 21, 12:38*pm, Philipp <(E-Mail Removed)> wrote:
> Hi
>
> I am wondering if there is any way that I can write a
> std_logic_vector(31 downto 0) into a file and there is should
> be written then as a HEX value? Is there something like
>
> * val = ABC(31 downto 0);
> * write(s, hex'(val));
>
> Thanks


Google for 'image_pkg' and Ben Cohen. That should produce a VHDL file
with a package that converts different types into a string. He has
both an 'image' and a 'heximage' function for std_logic_vector types.
Image produces a character for every bit in the vector (i.e. when
displayed/written it will look like binary). Heximage produces a
hexadecimal formatted string.
http://www.google.com/search?hl=en&q..._pkg+Ben+Cohen

Once you've got a string you can use standard text I/O facilities to
write out your file.

Kevin Jennings
 
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beky4kr@gmail.com
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      11-21-2008
On 21 *ובמבר, 21:04, Jonathan Bromley <(E-Mail Removed)>
wrote:
> On Fri, 21 Nov 2008 17:38:07 +0000, Philipp <(E-Mail Removed)> wrote:
> >I am wondering if there is any way that I can write a
> >std_logic_vector(31 downto 0) into a file and there is should
> >be written then as a HEX value? Is there something like

>
> > val = ABC(31 downto 0);
> > write(s, hex'(val));

>
> KJ is right, but you could also consider using the
> std_logic_textio package - originally from Synopsys,
> but fully supported by all serious simulators and,
> indeed, now incorporated into the latest VHDL standard.
>
> library ieee;
> use ieee.std_logic_1164.all; -- as usual
> use std.textio.all; -- as usual
> use ieee.std_logic_textio.all; -- this is the new part
>
> ....
> variable v: std_logic_vector (31 downto 0);
> variable L: line;
> ....
> write(L, v); -- writes 32 characters for the 32 bits
> hwrite(L, v); -- writes 8 hex digits or Xs
>
> read() and hread() too.
>
> Note that the value or variable must be an exact multiple
> of 4 elements, or else hwrite() won't work.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> (E-Mail Removed)://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.


Hi
I have a nice example of an AHB monitor. It monitors the data on an
AHB and writes a nice log.
h--p://bknpk.no-ip.biz/AHB_MON/ahb_mon_1.html

The code is available at:
h--p://bknpk.no-ip.biz/cgi-bin/InputForm_1.pl
AHB monitor.
-->file instantiation example:mcore.vhd

-->file the monitor:mon.vhd
 
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Tricky
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Posts: n/a
 
      11-24-2008
On 21 Nov, 19:04, Jonathan Bromley <(E-Mail Removed)>
wrote:
> On Fri, 21 Nov 2008 17:38:07 +0000, Philipp <(E-Mail Removed)> wrote:
> >I am wondering if there is any way that I can write a
> >std_logic_vector(31 downto 0) into a file and there is should
> >be written then as a HEX value? Is there something like

>
> > *val = ABC(31 downto 0);
> > *write(s, hex'(val));

>
> KJ is right, but you could also consider using the
> std_logic_textio package - originally from Synopsys,
> but fully supported by all serious simulators and,
> indeed, now incorporated into the latest VHDL standard.
>
> library ieee;
> use ieee.std_logic_1164.all; *-- as usual
> use std.textio.all; * * * * * -- as usual
> use ieee.std_logic_textio.all; -- this is the new part
>
> ....
> * variable v: std_logic_vector (31 downto 0);
> * variable L: line;
> ....
> * write(L, v); *-- writes 32 characters for the 32 bits
> * hwrite(L, v); -- writes 8 hex digits or Xs
>
> read() and hread() too.
>
> Note that the value or variable must be an exact multiple
> of 4 elements, or else hwrite() won't work.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> (E-Mail Removed)://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.


You forgot to mention ORead/OWrite if octal is your fettish.
 
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Tricky
Guest
Posts: n/a
 
      11-24-2008
On 21 Nov, 19:04, Jonathan Bromley <(E-Mail Removed)>
wrote:
> On Fri, 21 Nov 2008 17:38:07 +0000, Philipp <(E-Mail Removed)> wrote:
> >I am wondering if there is any way that I can write a
> >std_logic_vector(31 downto 0) into a file and there is should
> >be written then as a HEX value? Is there something like

>
> > *val = ABC(31 downto 0);
> > *write(s, hex'(val));

>
> KJ is right, but you could also consider using the
> std_logic_textio package - originally from Synopsys,
> but fully supported by all serious simulators and,
> indeed, now incorporated into the latest VHDL standard.
>
> library ieee;
> use ieee.std_logic_1164.all; *-- as usual
> use std.textio.all; * * * * * -- as usual
> use ieee.std_logic_textio.all; -- this is the new part
>
> ....
> * variable v: std_logic_vector (31 downto 0);
> * variable L: line;
> ....
> * write(L, v); *-- writes 32 characters for the 32 bits
> * hwrite(L, v); -- writes 8 hex digits or Xs
>
> read() and hread() too.
>
> Note that the value or variable must be an exact multiple
> of 4 elements, or else hwrite() won't work.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> (E-Mail Removed)://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.


Also, forgot to add:
Currently Hread/hwrite only works with busses that are multplies of 4
long, but I seem to remember something being mentioned that they were
dropping this restriction?
 
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