Go Back   Velocity Reviews > Newsgroups > VHDL
User Name
Password
Register FAQ Members List Calendar Search Today's Posts Mark Forums Read

Reply

VHDL - vhdl code generators ( crossposted in comp.hardware.fpga)

 
Thread Tools Search this Thread
Old 11-19-2008, 03:47 PM   #1
Default vhdl code generators ( crossposted in comp.hardware.fpga)


does anybody have a clear opinion about code generators ( c-> vhdl ,
matlab-> vhdl, etc..) that are around? Are they really irreplaceable
in complex applications (i.e DSP) as the vendors say?


abe
  Reply With Quote
Old 11-19-2008, 05:54 PM   #2
Tricky
 
Posts: n/a
Default Re: vhdl code generators ( crossposted in comp.hardware.fpga)
On 19 Nov, 15:47, abe <a.bergn...@gmail.com> wrote:
> does anybody have a clear opinion about code generators ( c-> vhdl ,
> matlab-> vhdl, etc..) that are around? Are they really irreplaceable
> in complex applications (i.e DSP) as the vendors say?


We recently had a talk from the guys at mathworks about Simulink.

From what I can tell, and from the opinion of the software and
hardware guys, is that the Software code generation is fairly mature
and pretty good.
We have done a simple project with VHDL code generation, and it does
work, but I wouldnt really call it readable, or maintainable in code
form, but the idea is all your source is the Simulink system diagrams.

Here is an example of the code generated for a multiplier:

signal input_a : unsigned(7 downto 0);
signal input_b : unsigned(7 downto 0);
signal mult_res : usngiend(15 downto 0);
signal mult_res_resize : unsigned(7 downto );
signal mult_res_register : unsigned(7 downto 0);
...
mult_res <= input_a * input_b;
mult_res_resize <= mult_res(15 downto ;

process(clk)
begin
if rising_edge(clk) then
mult_res_register <= mult_res_resize;
end if;
end process;

Now when you add that in with resize functions all over the page, it
quickly becomes unreadable. We had a simple system with about 4 fixed
point multipliers, and about 6 adders, and I wouldnt want to try and
re-organise it for efficiancy. If it was more complex, I wouldnt even
want to look at the output VHDL.

It is not meant to replace hand written code, it is meant to be a
system level specifcation that has the tools to generate code that can
be used to put onto an FPGA. It appears to be very useful at allowing
the user to specify what is software and what is hardware. I got the
feeling that for more complex systems, hand written VHDL would still
be far more maintainable and efficient for now. But it should work.

One point to note: you will need digital electronic knowledge to
ensure you create the hardware versions of the top level functions
properly.


Tricky
  Reply With Quote
Reply


Thread Tools Search this Thread
Search this Thread:

Advanced Search

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

vB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are Off
Pingbacks are Off
Refbacks are Off




SEO by vBSEO 3.3.2 ©2009, Crawlability, Inc.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46