Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > DOWNTO versus TO keyword on Component instantiation

Thread Tools

DOWNTO versus TO keyword on Component instantiation
Posts: n/a

Does anyone know about the following error in Modelsim ?

** Error: xxx.vhd(2435): (vcom-1012) Slice range direction (to) does
not match slice prefix dire
ction (downto).

The slice range direction on the concerned port are identical on the
entity and on the component declaration (DOWNTO keyword) but I cant
use slice range direction (TO) in the assigned signal.
If I set TO every where is does not work better. The only solution is
using "downto" everywhere...

Is it a VHDL restriction ?

Reply With Quote
jeppe jeppe is offline
Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 348
Well be sure that these rules followed:

Highnumber DOWNTO Lownumber like: 10 DOWNTO 0

Lownumber TO Highnumber like: 0 TO 10

Reply With Quote

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off

Similar Threads
Thread Thread Starter Forum Replies Last Post
Re: Mozilla versus IE versus Opera versus Safari Peter Potamus the Purple Hippo Firefox 0 05-08-2008 12:56 PM
equal? versus eql? versus == versus === verus <=> Paul Butcher Ruby 12 11-28-2007 06:06 AM
ARRAY(n DOWNTO 0) OF STD_LOGIC_VECTOR(m DOWNTO 0) - VHDL freitass Hardware 0 11-01-2007 03:44 PM
signed(12 downto 0) to signed (8 downto 0) kyrpa83 VHDL 1 10-17-2007 06:58 PM
Explicit instantiation of STL vector demands explicit instantiation of all the templates it using internally. C++ 1 12-25-2006 03:51 PM