|
|
|
|
|
|||||||
 |
VHDL - Re: Aligned PLL clocks in RTL simulation |
|
|
Thread Tools | Search this Thread |
11-17-2008, 11:16 PM
|
#1 |
Re: Aligned PLL clocks in RTL simulation
Jonathan Bromley wrote:
> I swapped-in > much simpler, but perfectly adequate in-house models and > got x10 simulation speedup. Ditto! Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266 Mark McDougall |
|
|
|
| Thread Tools | Search this Thread |
|
|
Similar Threads
|
||||
| Thread | Thread Starter | Forum | Replies | Last Post |
| Simulation question Issue | Rahul | MCITP | 9 | 06-30-2008 09:53 PM |
| Simulation in 70-444 | CorreiaLC | MCITP | 0 | 10-11-2007 07:18 PM |
| Post-Route Simulation does not give output for the first clock cycle Options | velocityreviews | Software | 0 | 04-17-2007 05:47 PM |
| simulation | Tom | MCITP | 0 | 04-05-2007 01:40 AM |
| Wanna site names that provide simulation tests for A+ | raisasheikh@lycos.com | A+ Certification | 0 | 09-06-2005 07:50 PM |
