Re: Aligned PLL clocks in RTL simulation

In comp.arch.fpga Jonathan Bromley <> wrote:
....

> Opinions/rants/insults welcomed. Thanks in advance.

I have a similar problem:
20 MHz "clock_in", internal used multiplied by five, used als "clk" and
also used doubled as "clkx2"
The clock_in is not used.
I use this:
`ifdef __ICARUS__
reg clkx2 = 0;
reg clk = 0;

always @(posedge clk_in)
{clk, clkx2} <= {clk, clkx2} + {2{clk_in}};
assign alu_ctl_bits[`CMD_RST] = 1'b0;
`else
wire clk, clkx2;

clk100 dcm0
(
.CLKIN_IN(clk_in),
.RST_IN(alu_ctl_cmd[`CMD_RST]),
.CLKFX_OUT(clk80),
.CLKIN_IBUFG_OUT()
);

DCM dcmac (
.CLKIN(clk80),
.CLKFB(clkx2),
.RST(alu_ctl_cmd[`CMD_RST]),
.CLK0(clkacdcm),
.CLK2X(clkacx2dcm),
.LOCKED(alu_ctl_bits[`CMD_RST]));
BUFG clkbuf(.I(clkacdcm),.O(clk));
BUFG clkx2buf(.I(clkacx2dcm),.O(clkx2));
`endif // !`ifdef __ICARUS__

For simulation I now use clk_in == clk
--
Uwe Bonnes

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Uwe Bonnes