FOR LOOP in VHDL testbench?

I have the following VHDL testbench.
How do i make a for loop that goes through :L_ADDRESS (4 down to 0)"
I just want to be able to see L_ADDRESS change every 100ns in the wave viewer?
---------------------------------------------------------------------
-- VHDL Test Bench Created from source file SDPRAM.vhd -- 07-MAY-2008 01:09:40

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS

COMPONENT SDPRAM
PORT(
L_CLK : IN std_logic;
L_ADDRESS : IN std_logic_vector(4 downto 0);
L_CS : IN std_logic;
L_WE : IN std_logic;
L_OE : IN std_logic;
C_CLK : IN std_logic;
C_ADDRESS : IN std_logic_vector(4 downto 0);
C_CS : IN std_logic;
C_WE : IN std_logic;
C_OE : IN std_logic;
L_DATA : INOUT std_logic_vector(15 downto 0);
C_DATA : INOUT std_logic_vector(15 downto 0)
);
END COMPONENT;

SIGNAL L_CLK : std_logic;
SIGNAL L_ADDRESS : std_logic_vector(4 downto 0);
SIGNAL L_DATA : std_logic_vector(15 downto 0);
SIGNAL L_CS : std_logic;
SIGNAL L_WE : std_logic;
SIGNAL L_OE : std_logic;
SIGNAL C_CLK : std_logic;
SIGNAL C_ADDRESS : std_logic_vector(4 downto 0);
SIGNAL C_DATA : std_logic_vector(15 downto 0);
SIGNAL C_CS : std_logic;
SIGNAL C_WE : std_logic;
SIGNAL C_OE : std_logic;

BEGIN

-- Please check and add your generic clause manually
uut: SDPRAM PORT MAP(
L_CLK => L_CLK,
L_ADDRESS => L_ADDRESS,
L_DATA => L_DATA,
L_CS => L_CS,
L_WE => L_WE,
L_OE => L_OE,
C_CLK => C_CLK,
C_ADDRESS => C_ADDRESS,
C_DATA => C_DATA,
C_CS => C_CS,
C_WE => C_WE,
C_OE => C_OE
);

Clock : PROCESS
BEGIN
L_CLK <= '1';
wait for 41 ns;
L_CLK <= '0';
wait for 41 ns;
END PROCESS;






END;

Daryl