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VHDL - testbench

 
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Old 11-17-2008, 06:28 AM   #1
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I wrote a testbench for a 4-bit syn counter.
i initialised a 4-bit variable inp ( declared as inout )to 0 and then
tried to increment it in a loop as
inp=inp + 1; But this statement is creating problems


whereismelvin@gmail.com
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Old 11-17-2008, 09:18 AM   #2
Tricky
 
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Default Re: testbench
On 17 Nov, 06:28, whereismel...@gmail.com wrote:
> I wrote a testbench for a 4-bit syn counter.
> i initialised a 4-bit variable inp ( declared as inout )to 0 and then
> tried to increment it in a loop as
> inp=inp + 1; * But this statement is creating problems


Plase post the code that is causing problems.


Tricky
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