Signal Conditional Assignment ?

guylewis

Junior Member

Join Date: Nov 2008

Posts: 3

11-15-2008

Can anyone help with explaining how the statement below works? I'm confused as to why you AND data_out?

Statement in question
-------------------------
read_mux_out <= A_REP(to_std_logic((((std_logic_vector'("000000000 000000000000000000000") & (address)) = std_logic_vector'("0000000000000000000000000000000 0")))), 13) AND data_out;

Thanks for any help
Guy

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