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#1 |
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I have following code:
library IEEE; use IEEE.STD_LOGIC_1164.all; package my_pkg is COMPONENT my_comp PORT( clk : IN STD_LOGIC; a : IN STD_LOGIC; b : OUT STD_LOGIC; c : IN STD_LOGIC; d : INOUT STD_LOGIC; ); END my_comp; END my_pkg; During compilation, I'm getting error: near "library": syntax error What am I missing here? thanks, Anand AnandA |
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#2 |
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Posts: n/a
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AnandA wrote:
> During compilation, I'm getting error: > near "library": syntax error > > What am I missing here? -- Proper syntax library ieee; use ieee.std_logic_1164.all; package my_pkg is component my_comp is port( clk : in std_logic; a : in std_logic; b : out std_logic; c : in std_logic; d : inout std_logic); end component my_comp; end my_pkg; consider: 1. A vhdl-aware editor 2. direct instances instead of components 3. not using inout ports Mike Treseler |
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