shift register

I have written a vhdl code in xilinx for a serial in serial out shift
register. It is modelled using 4 d flip flops. The problem is that the
output waveform is coming as an undefined signal.

--D FLIP FLOP FILE

entity dff is
    Port ( d : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           clr : in  STD_LOGIC;
           q : out  STD_LOGIC);
end dff;

architecture Behavioral of dff is
begin
	process (clk, clr)
	begin
		if clr = '0' then
			q <= '0';
		elsif clk 'event and clk = '1'
			q <= d;
		end if;
	end process;
end Behavioral;

-- SHIFT REGISTER FILE

entity pmshreg is
    Port ( inp : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           clr : in  STD_LOGIC;
           outp : out  STD_LOGIC);
end pmshreg;

architecture Behavioral of pmshreg is
component dff is
	Port ( d : in STD_LOGIC;
			 clk : in STD_LOGIC;
			 clr : in STD_LOGIC;
			 q : out STD_LOGIC);
end component;
signal temp: STD_LOGIC_VECTOR (4 downto 0);
begin
	temp(4) <= inp;
	lab: for i in 0 to 3 generate
				ins: dff port map (temp(4 - i), clk, clr, temp(4 - (i + 1)));
		  end generate;
	outp <= temp(0);
end Behavioral;

If anybody can help, thanks...

coderyogi

On 14 Nov., 18:49, coderyogi <zape...@gmail.com> wrote:
> I have written a vhdl code in xilinx for a serial in serial out shift
> register. It is modelled using 4 d flip flops. The problem is that the
> output waveform is coming as an undefined signal.
[..]
> If anybody can help, thanks...

First of all, please use named associations

dff port map (d=>temp(4 - i), clk=>clk, clr=>clr, q=>temp(4 - (i +
1)))

to avoid problems with implicit signal association.

The be please precise about the output, is your result uninitialised
'U' or unknown 'X'.
Then tell more about your testbench that you use simulating the shift
register, it is most likely, that your testbench contains the error.

regards Thomas

Thomas Stanka

[jeppe]

1) Its works nicely at my computer - I noticed that CLR is active low - could this be a problem in your simulation.

2) Theres more efficient ways to descripe this functionality but I quess that this not an issue here.

Regards
Jeppe

jeppe

On Nov 15, 3:21 pm, Thomas Stanka <usenet_nospam_va...@stanka-web.de>
wrote:
> On 14 Nov., 18:49, coderyogi <zape...@gmail.com> wrote:
>
> > I have written a vhdl code in xilinx for a serial in serial out shift
> > register. It is modelled using 4 d flip flops. The problem is that the
> > output waveform is coming as an undefined signal.
> [..]
> > If anybody can help, thanks...
>
> First of all, please use named associations
>
> dff port map (d=>temp(4 - i), clk=>clk, clr=>clr, q=>temp(4 - (i +
> 1)))
>
> to avoid problems with implicit signal association.
>
> The be please precise about the output, is your result uninitialised
> 'U' or unknown 'X'.
> Then tell more about your testbench that you use simulating the shift
> register, it is most likely, that your testbench contains the error.
>
> regards Thomas

Well output is coming as uninitialised U.

--testbench

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 9.1i
-- \ \ Application : ISE
-- / / Filename : pmtest_shreg.vhw
-- /___/ /\ Timestamp : Sat Nov 15 20:28:40 2008
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name: pmtest_shreg
--Device: Xilinx
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY pmtest_shreg IS
END pmtest_shreg;

ARCHITECTURE testbench_arch OF pmtest_shreg IS
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

COMPONENT pmshreg
PORT (
inp : In std_logic;
clk : In std_logic;
clr : In std_logic;
outp : Out std_logic
);
END COMPONENT;

SIGNAL inp : std_logic := '1';
SIGNAL clk : std_logic := '0';
SIGNAL clr : std_logic := '0';
SIGNAL outp : std_logic := '0';

constant PERIOD : time := 200 ns;
constant DUTY_CYCLE : real := 0.5;
constant OFFSET : time := 0 ns;

BEGIN
UUT : pmshreg
PORT MAP (
inp => inp,
clk => clk,
clr => clr,
outp => outp
);

PROCESS -- clock process for clk
BEGIN
WAIT for OFFSET;
CLOCK_LOOP : LOOP
clk <= '0';
WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
clk <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;

PROCESS
BEGIN
-- ------------- Current Time: 285ns
WAIT FOR 285 ns;
clr <= '1';
-- -------------------------------------
-- ------------- Current Time: 485ns
WAIT FOR 200 ns;
inp <= '0';
-- -------------------------------------
-- ------------- Current Time: 885ns
WAIT FOR 400 ns;
inp <= '1';
-- -------------------------------------
-- ------------- Current Time: 1685ns
WAIT FOR 800 ns;
inp <= '0';
-- -------------------------------------
WAIT FOR 515 ns;

END PROCESS;

END testbench_arch;

Rajneesh ....

"coderyogi" <> wrote in message
news:ae6b81b8-4f83-4f50-bb3c-...
>I have written a vhdl code in xilinx for a serial in serial out shift
> register. It is modelled using 4 d flip flops. The problem is that the
> output waveform is coming as an undefined signal.
>
<snip>
> If anybody can help, thanks...

One of two things:
1. You didn't run the simulation.
2. Your testbench doesn't properly control the 'clk', 'inp' and 'clr'
inputs.

Below is a testbench that works.

library ieee;
use ieee.std_logic_1164.all;
entity tb_pmshreg is
end tb_pmshreg;

architecture rtl of tb_pmshreg is
signal inp: std_logic;
signal clk: std_logic := '0';
signal clr: std_logic;
signal outp: std_logic;
signal Sim_Complete: std_logic := '0';
begin
clk <= not(Sim_Complete) and not(clk) after 5 ns;
process
begin
clr <= '1';
inp <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
inp <= '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
inp <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
Sim_Complete <= '1';
wait;
end process;
The_pmshreg : entity work.pmshreg port map(
inp => inp,
clk => clk,
clr => clr,
outp=> outp);
end rtl;

KJ

On 15 Nov., 16:08, "Rajneesh ...." <rajneeshcha...@gmail.com> wrote:

> Well output is coming as uninitialised U.

Your testbench and code contain no obvious error (to me) that explains
this output.
But your code is not configured, you should double check, that your
simulation uses your dff(and nothing else). It would be a good idea to
run simulation and trace the internal signals to ensure your dff is
correctly connected and proper stimulated.
Also check the clk generated from your process. I'm not shure if the
multiplication with 0.5 is correctly performed for type time.

regards Thomas

Thomas Stanka

On Nov 15, 10:08*am, "Rajneesh ...." <rajneeshcha...@gmail.com> wrote:
> On Nov 15, 3:21 pm, Thomas Stanka <usenet_nospam_va...@stanka-web.de>
> wrote:
>
> Well output is coming as uninitialised U.
>

It is only 'U' at the start of simulation (i.e. t=0). Once you
actually run the simulator you would see that it changes to 0 on the
next simulator delta cycle (which is also at t=0). Add the input/
output signals to the wave window, run the simulator for 1 us and see
that it is working as one would expect.

KJ

KJ

coderyogi wrote:
> I have written a vhdl code in xilinx for a serial in serial out shift
> register. It is modelled using 4 d flip flops. The problem is that the
> output waveform is coming as an undefined signal.
>
> --D FLIP FLOP FILE
>
> entity dff is
> Port ( d : in STD_LOGIC;
> clk : in STD_LOGIC;
> clr : in STD_LOGIC;
> q : out STD_LOGIC);
> end dff;
>
> architecture Behavioral of dff is
> begin
> process (clk, clr)
> begin
> if clr = '0' then
> q <= '0';
> elsif clk 'event and clk = '1'
--
THEN ---------------------------------
--
> q <= d;
> end if;
> end process;
> end Behavioral;

Mike Treseler