using both rising edge and falling edge of signal

i generated a signal that has a frequency of 100 kHz using master
clock.
and now i want to use both the rising and falling edge of this signal
as a condition in states. will this be synthesizable. or i need to use
the level triggering instead of using edge trigerring.

denish

On 14 Nov, 13:51, denish <dinesh.twanab...@gmail.com> wrote:
> *i generated a signal that has a frequency of 100 kHz using master
> clock.
> and now i want to use both the rising and falling edge of this signal
> as a condition in states. will this be synthesizable. or i need to use
> the level triggering instead of using edge trigerring.

Edge triggering implies it is a clock. If you're thinking about using
this on an FPGA you'll run into 2 main problems:

1. FPGAs like to run all their registers off global clocks
2. FPGAs only like to use a single edge of the clock.

I would recommend using your 100KHz signal as an enable to registers,
not actually clocking them.

Tricky

On Nov 14, 3:51*pm, denish <dinesh.twanab...@gmail.com> wrote:
> *i generated a signal that has a frequency of 100 kHz using master
> clock.
> and now i want to use both the rising and falling edge of this signal
> as a condition in states. will this be synthesizable. or i need to use
> the level triggering instead of using edge trigerring.

For the most maintainable and safe code, don't use this signal to
clock your registers directly. Rather, clock all FFs with you FPGA's
(I assume you're not developing an ASIC) main clock, and sample this
signal, detect its rising and falling edges and use this sampled
information as an enable.

Eli

Eli Bendersky

denish wrote:
> i generated a signal that has a frequency of 100 kHz using master
> clock.
> and now i want to use both the rising and falling edge of this signal
> as a condition in states. will this be synthesizable. or i need to use
> the level triggering instead of using edge trigerring.

I would use only the master clock, like this

master clk _-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-

gen signal -------________--------________-------

shifter 0 1 3 3 2 0 0 0 1 3 3 3 2 0 0 0 1 3 3

rise ___--____________--______________--____

fall _________--______________--____________

-- Mike Treseler

Mike Treseler

[jeppe]

How about using a 200 kHz master clock internal - just a suggestion

Jeppe

jeppe

On Nov 14, 9:01*am, Tricky <Trickyh...@gmail.com> wrote:
> 1. FPGAs like to run all their registers off global clocks
> 2. FPGAs only like to use a single edge of the clock.
>
> I would recommend using your 100KHz signal as an enable to registers,
> not actually clocking them.

I agree with this except #2. FGPAs can use either edge of a clock just
as easily, just not both edges on the same register. Nor is this
limitation unique to FPGAs.

There are ways to implement dual clock edged behavior using single
clock edged registers, but that is getting too far off topic.

Like the other posters said, sample and detect rising and falling
edges of the slower clock using the faster, master clock.

Andy

Andy