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Signal Generator code

 
 
coderyogi
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      11-13-2008
I've written a vhdl code in xilinx that generates an output waveform
based on the input clock. The problem i'm getting is that the code is
running only for the positive edge of the clock pulse whereas i've
coded it (i hope) to work for both positive as well as negative edges
of the clock pulse.

What i mean is that only that portion of the code is executing when
clock is = 1.

Code:
entity sig_gen is
    Port ( clk : in  STD_LOGIC;
			  outp : out  STD_LOGIC);
end sig_gen;

architecture Behavioral of sig_gen is
begin
	process (clk)
	variable temp1, temp2, temp3, temp4: integer:= 0;
	begin
		if (clk = '1') then
			temp1 := temp1 + 1;
			temp2 := temp2 + 1;
			if (temp1 = 1 and temp2 = 1) then
				outp <= '1';
			elsif (temp2 = 3) then
				temp1 := 0;
				temp2 := 0;
				temp3 := 0;
				temp4 := 0;
				outp <= '0';
			else
				outp <= '0';
			end if;
		else
			temp3 := temp3 + 1;
			temp4 := temp4 + 1;
			if (temp3 = 2 and temp4 = 2) then
				outp <= '1';
			else
				outp <= '0';
			end if;
		end if;
	end process;
end Behavioral;
Any help would be appreciated...
 
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kennheinrich@sympatico.ca
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Posts: n/a
 
      11-14-2008
On Nov 13, 2:07*pm, coderyogi <(E-Mail Removed)> wrote:
> I've written a vhdl code in xilinx that generates an output waveform
> based on the input clock. The problem i'm getting is that the code is
> running only for the positive edge of the clock pulse whereas i've
> coded it (i hope) to work for both positive as well as negative edges
> of the clock pulse.
>
> What i mean is that only that portion of the code is executing when
> clock is = 1.
>
>
Code:
>
> entity sig_gen is
> * * Port ( clk : in *STD_LOGIC;
> * * * * * * * * * * * * * outp : out *STD_LOGIC);
> end sig_gen;
>
> architecture Behavioral of sig_gen is
> begin
> * * * * process (clk)
> * * * * variable temp1, temp2, temp3, temp4: integer:= 0;
> * * * * begin
> * * * * * * * * if (clk = '1') then
> * * * * * * * * * * * * temp1 := temp1 + 1;
> * * * * * * * * * * * * temp2 := temp2 + 1;
> * * * * * * * * * * * * if (temp1 = 1 and temp2 = 1) then
> * * * * * * * * * * * * * * * * outp <= '1';
> * * * * * * * * * * * * elsif (temp2 = 3) then
> * * * * * * * * * * * * * * * * temp1 := 0;
> * * * * * * * * * * * * * * * * temp2 := 0;
> * * * * * * * * * * * * * * * * temp3 := 0;
> * * * * * * * * * * * * * * * * temp4 := 0;
> * * * * * * * * * * * * * * * * outp <= '0';
> * * * * * * * * * * * * else
> * * * * * * * * * * * * * * * * outp <= '0';
> * * * * * * * * * * * * end if;
> * * * * * * * * else
> * * * * * * * * * * * * temp3 := temp3 + 1;
> * * * * * * * * * * * * temp4 := temp4 + 1;
> * * * * * * * * * * * * if (temp3 = 2 and temp4 = 2) then
> * * * * * * * * * * * * * * * * outp <= '1';
> * * * * * * * * * * * * else
> * * * * * * * * * * * * * * * * outp <= '0';
> * * * * * * * * * * * * end if;
> * * * * * * * * end if;
> * * * * end process;
> end Behavioral;
>
>
>
> Any help would be appreciated...


In VHDL, you're allowed to write almost any crazy thing you want and
it will simulate. But only a small subset of the things you can
possibly write actually make sense to get mapped into hardware. A
counter (or other flopped logic) that runs on both clock edges is one
of those describable but not buildable things.

The other mistake you've made is that (for simulation only: do NOT try
to build this for real) you should be using a template like this:

process (clk)
begin
if rising_edge(clk) then
... insert rising edge stuff here
end if;
if falling_edge(clk) then
.. insert falling edge here
end if;
end process;

where rising edge is more or less a shorthand for (clk'event and clk =
'1').

But again, this is for illustration only. Do not get into the habit of
writing double-edge processes at all. Expunge all references to them
in your mind now. Only do this to show a professor that you "get" some
nuance of how the language works, or if you're writing a testbench
that you know is intended only to run in a simulator.

- Kenn
 
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