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VHDL - Coding style to improve timing

 
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Old 11-13-2008, 02:54 PM   #1
Default Coding style to improve timing


Hi,
I am currently having problems closing timing on a design and I was hoping someone could advise me 2 different coding styles.

If I have some logic described as shown below in 2 different forms, which would be the most efficient as regards timing, and why?

if (signal_1 and signal_2(1) and not signal_3) = '1' then
--do something
end if;


OR


if (signal_1 = '1') then
if (signal_2(1) = '1') then
if (signal_3 = '0') then
--do something
end if;
end if;
end if;


Many thanks for any advise. i ask because I have timing problems on certain paths, with only a small bit of negative slack to overcome. I am thinking that if I change the coding style in certain places, maybe it may help.


Thanks


Ardni

Last edited by Ardni : 11-13-2008 at 03:00 PM.
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