Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > floatfixlib synthesis

Reply
Thread Tools

floatfixlib synthesis

 
 
universeee universeee is offline
Junior Member
Join Date: Apr 2008
Posts: 3
 
      11-12-2008
I ve written a code below which can be simulated but cannot be synthesized in Leonardo Spectrum ver. 2007a.37

Here is the code
Code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library floatfixlib;
use floatfixlib.math_utility_pkg.all;
use floatfixlib.fixed_pkg.all;

entity test is
	port(a,b: in sfixed(7 downto -6);
	     c: out sfixed(8 downto -6));
end test;

architecture testing of test is
begin

    c <= a+b;      

end testing;
Here is the synthesis error
Code:
-- Reading vhdl file C:/Documents and Settings/batur/Desktop/test.vhd into library work
"C:/Documents and Settings/batur/Desktop/test.vhd",line 5: Warning, math_utility_pkg is not declared in library floatfixlib.
"C:/Documents and Settings/batur/Desktop/test.vhd",line 6: Warning, fixed_pkg is not declared in library floatfixlib.
"C:/Documents and Settings/batur/Desktop/test.vhd",line 9: Error, sfixed is not a known type.
"C:/Documents and Settings/batur/Desktop/test.vhd",line 10: Error, sfixed is not a known type.
"C:/Documents and Settings/batur/Desktop/test.vhd",line 9: Error, sfixed requires 0 index values.
"C:/Documents and Settings/batur/Desktop/test.vhd",line 10: Error, sfixed requires 0 index values.
Error in file C:/Documents and Settings/batur/Desktop/test.vhd.
-- Error found in VHDL source

It says library error. Is Fixed point library "floatfixlib" synthesizable or not???
How can we write fixed point code that is synthesizable?
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
SOS! newbie question about synthesizable VHDL : synthesis run successfully but post-synthesis failed... walala VHDL 4 09-09-2003 08:41 AM
what are the possible reasons that successful pre-synthesis simulation + successful synthesis = failed post-synthes walala VHDL 4 09-08-2003 01:51 PM
Slow Synthesis Jeremy Pyle VHDL 5 07-23-2003 04:25 AM
std_logic_vector port doesn't work after synthesis. Mike VHDL 3 07-09-2003 09:10 PM
Synthesis of STD_LOGIC Christopher Bunk VHDL 2 07-04-2003 07:08 AM



Advertisments