output TY = = -1.#INF ???

Hi Guyz


i have a filter as below:

-------------------------------------------------------------
--Filter
-------------------------------------------------------------
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Std_logic_unsigned.all;
use IEEE.numeric_std.all;
use IEEE.Std_logic_arith.all;

entity filter is
port ( x : in real;
CLK : in natural;
y : out real);
end filter;

architecture behavioural of filter is

type Value_Table is array (Natural range 1 to 10) of real;
signal Value : Value_Table;

begin


process(x, CLK)
begin

if CLK = 1 then Value(1) <= x; y <= Value(1);
elsif CLK = 2 then Value(2) <= x; y <= Value(2) + (0.6*Value(1));
elsif CLK = 3 then Value(3) <= x; y <= Value(3) + (0.6*Value(2)) + (-0.16*Value(1));
elsif CLK = 4 then Value(4) <= x; y <= Value(4) + (0.6*Value(3)) + (-0.16*Value(2));
elsif CLK = 5 then Value(5) <= x; y <= Value(5) + (0.6*Value(4)) + (-0.16*Value(3));
elsif CLK = 6 then Value(6) <= x; y <= Value(6) + (0.6*Value(5)) + (-0.16*Value(4));
elsif CLK = 7 then Value(7) <= x; y <= Value(7) + (0.6*Value(6)) + (-0.16*Value(5));
elsif CLK = 8 then Value( <= x; y <= Value( + (0.6*Value(7)) + (-0.16*Value(6));
elsif CLK = 9 then Value(9) <= x; y <= Value(9) + (0.6*Value() + (-0.16*Value(7));
elsif CLK = 10 then Value(10) <= x; y <= Value(10) + (0.6*Value(9)) + (-0.16*Value();
end if;

end process;
end behavioural;

-------------------------------------------------------------
--Testbench
-------------------------------------------------------------

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Std_logic_unsigned.all;
use IEEE.numeric_std.all;
use IEEE.Std_logic_arith.all;

entity filter_add is
port (TY: out real);
End filter_add;

architecture behavioural of filter_add is
component filter is
port ( x : in real;
CLK : in natural;
y : out real);
end component;

signal TX : real;
signal CLK : natural;

type Table is array (Natural range 1 to 10) of real;
constant Lookup: Table :=
(0.12, 0.50, 0.80, 0.6, -0.16, 0.0, -0.11, -0.56, -0.68, -0.24);

BEGIN

u1: component filter
port map (x=>TX, CLK=>CLK, y=>TY);

process
begin

for i in 1 to 10 loop

CLK <= i;
TX <= Lookup(i);
wait for 10 ns;

end loop;
end process;
end behavioural;


Using the above testbench my output TY = = -1.#INF in the waveforms. What am I doing wrong?
-----------------------------------------------------------------------
Thanks..........

wales_1986