On Nov 11, 7:11*am, sebs <(E-Mail Removed)> wrote:

> Hey,

>

> I have a unsigned to std_logic_vector conversion and I get the

> following error:

>

> "to_stdLogicVector can not have such operands in this context."

>

> I'm using Xilinx EDK 8.1

>

> Here is some of my code to explain where the errror occurs.

>

> library ieee;

> use ieee.std_logic_1164.all;

> use ieee.numeric_std.all;

>

> * M_ABus * * : out std_logic_vector(0 to 31);

>

> *signal row_cnt * * *: unsigned(0 to 9);

> *signal row_cnt_en * : std_logic;

> *signal row_rst * * *: std_logic;

>

> addr_counter : process(PLB_Clk, PLB_Rst)

> *begin

> * *if PLB_Clk'event and PLB_Clk = '1' then

> * * *if row_cnt_en = '1' then

> * * * *row_cnt <= row_cnt + 1;

> * * *end if;

> * *end if;

> * *if (PLB_RST or row_rst) = '1' then

> * * *row_cnt <= (others => '0'); * -- 768-1

> * *end if;

> *end process;

>

> * M_ABus(11 to 20) <= to_stdLogicVector(row_cnt); * -- the error

> occurs in this line.

>

> Hope someone can help me with this.

>

> Sebastian
The function To_StdLogicVector() is defined for BIT_VECTOR, and

STD_ULOGIC_VECTOR only. But you're passing it an UNSIGNED. Even

though STD_UNLOGIC_VECTOR smells kind of like an UNSIGNED, it's a

different type. However, the element types of std_logic_vector and

unsigned are both std_logic though, so you could just pass them

element by element:

for i in 11 to 20 generate

m_ABus(i) <= row_cnt(i-11);

end generate;

I might be missing some obvious library conversion function, on the

other hand

- Kenn