"Value of index is not static"

Default Compiling Error : "Value of index is not static"
Hi,
I'm implementing a simple ripple carry adder using instances of a
simple adder (called CLA...that works..).The ripple carry adder is
generic , N is the bit widht.
Unfortunately when I loop to generate the simple adders ("CLA"
components..) ,
I receive 2 errors : value "I" is not static (at the component "as":
entity) , and value of index is not static(at aLess1: entity) .


Code:



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity RCA is

generic(N:integer:=4);

Port ( A : in STD_LOGIC_VECTOR(N-1 downto 0);--nel caso da 3 a 0
(cioè 4)
B : in STD_LOGIC_VECTOR(N-1 downto 0);
S : out STD_LOGIC_VECTOR(N-1 downto 0);
Carry_in : in STD_LOGIC;--un solo bit di uscita globale
Carry_out : out STD_LOGIC);--un solo bit di uscita globale
end RCA;

architecture behavioral of RCA is

signal c : std_logic_vector(N-1 to 0); -- internal carry signal

COMPONENT CLA --

GENERIC (N: INTEGER := 32);

PORT ( a : IN UNSIGNED ((N-1) DOWNTO 0);
b : IN UNSIGNED ((N-1) DOWNTO 0);
c_in : IN STD_LOGIC;
s : OUT UNSIGNED ((N-1) DOWNTO 0);
c_out : OUT STD_LOGIC;
overflow : OUT STD_LOGIC

);
END COMPONENT;





begin

a0: entity CLA generic map(1) port
map(A(0)=>a(0),B(0)=>b(0),C_in=>Carry_in,C_out=>c( 0),S(0)=>S(0));


middle: for I in 1 to N-2 generate

as: entity CLA generic map(1) port map(A(I)=>a(I),B(I)=>b(I),C_in=>
c(I-1),C_out=>c(I), S(I)=>s(I));

end generate middle;



aLess1: entity CLA generic map(1) port
map(A(N-1)=>a(N-1),B(N-1)=>b(N-1),C_in=>
c(N-2) ,C_out=>Carry_out,S(N-1)=>s(N-1));



end Behavioral;





Could you help me please?
Thanks a lot in advance..

andrezz

"andrezz" <> wrote in message
news:aa20f598-c2f4-4b2d-8683-...

> I receive 2 errors : value "I" is not static (at the component "as":
> entity) , and value of index is not static(at aLess1: entity) .

On the component definition you define the vector ranges as (N-1) downto 0
but when you go to instantiate it you're calling the port A(I) (as an
example). You need to assign the entire 'A' vector ('B' vector and 'S'
vector). I think what you're trying to get is...

middle: for I in 1 to N-2 generate

as: entity CLA generic map(1) port map(A=>a(I),B=>b(I),C_in=>
c(I-1),C_out=>c(I), S=>s(I));

end generate middle;

KJ

KJ

On Nov 10, 11:32*am, "KJ" <kkjenni...@sbcglobal.net> wrote:
> "andrezz" <bugp...@gmail.com> wrote in message
>
> news:aa20f598-c2f4-4b2d-8683-...
>
> > I receive 2 errors : value "I" is not static (at the component "as":
> > entity) , and value of index is not static(at aLess1: entity) .
>
> On the component definition you define the vector ranges as (N-1) downto 0
> but when you go to instantiate it you're calling the port A(I) (as an
> example). *You need to assign the entire 'A' vector ('B' vector and 'S'
> vector). *I think what you're trying to get is...
>
> middle: for I in 1 to N-2 generate
>
> as: entity CLA generic map(1) port map(A=>a(I),B=>b(I),C_in=>
> c(I-1),C_out=>c(I), S=>s(I));
>
> end generate middle;
>
> KJ

KJ may be on the right track, but it's more complicated than that.
Your ports are not bits, but vectors of length 1 (with the only index
being 0). Slight difference. The only way I know of to convert from a
bit to a one-bit vector is with positional notation.

You probably need port assignments something like:

A => (0=>a(i)), b => (0=>b(i)), etc.

In other words, port A is associated to a vector that has bit 0
assigned to a(i).

Andy

Andy

> > vector). I think what you're trying to get is...
> >
> > middle: for I in 1 to N-2 generate
> >
> > as: entity CLA generic map(1) port map(A=>a(I),B=>b(I),C_in=>
> > c(I-1),C_out=>c(I), S=>s(I));
> >
> > end generate middle;
> >
> > KJ
>
> KJ may be on the right track, but it's more complicated than that.
> Your ports are not bits, but vectors of length 1 (with the only index
> being 0). Slight difference. The only way I know of to convert from a
> bit to a one-bit vector is with positional notation.
>
> You probably need port assignments something like:
>
> A => (0=>a(i)), b => (0=>b(i)), etc.
>
> In other words, port A is associated to a vector that has bit 0
> assigned to a(i).
>

Good catch. Another alternative for the port mapping is

A(0) =>a(i), b(0) => b(i), etc.

KJ

KJ

On 10 Nov, 21:04, "KJ" <kkjenni...@sbcglobal.net> wrote:
> > > vector). I think what you're trying to get is...
>
> > > middle: for I in 1 to N-2 generate
>
> > > as: entity CLA generic map(1) port map(A=>a(I),B=>b(I),C_in=>
> > > c(I-1),C_out=>c(I), S=>s(I));
>
> > > end generate middle;
>
> > > KJ
>
> > KJ may be on the right track, but it's more complicated than that.
> > Your ports are not bits, but vectors of length 1 (with the only index
> > being 0). Slight difference. The only way I know of to convert from a
> > bit to a one-bit vector is with positional notation.
>
> > You probably need port assignments something like:
>
> > A => (0=>a(i)), b => (0=>b(i)), etc.
>
> > In other words, port A is associated to a vector that has bit 0
> > assigned to a(i).
>
> Good catch. *Another alternative for the port mapping is
>
> A(0) =>a(i), b(0) => b(i), etc.
>
> KJ

thank you..solved..

andrezz