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VHDL - Unsigned subtraction

 
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Old 11-06-2008, 03:24 PM   #1
Default Unsigned subtraction


Hi guys..
I have to use a carry look ahead adder component (32bit), to implement a module able to perform addition (both signed and unsigned) , subtraction(signed and unsigned).
The only issue is the unsigned subtraction...how do I can do it? (in signed case I convert the number to 2's complement)..
thanks in advance..

andrew r.


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Old 11-06-2008, 06:35 PM   #2
jeppe
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Hi
I got a feeling that the signed/unsigned part comes free - if you just implement the circuit for addition / subtraction.

You can find a lot of inspiration at this site.
http://tima-cmp.imag.fr/~guyot/Cours...ish/Adspec.htm

Jeppe


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Old 11-06-2008, 08:14 PM   #3
andrew_ross
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Thanks a lot..I'll try right right now..


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